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[svsim] Expose further verilator options for trace file name and simulation speed optimization #3985

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merged 1 commit into from
Apr 10, 2024

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kammoh
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@kammoh kammoh commented Apr 10, 2024

  • Changed TraceStyle.Vcd to include a trace file name
  • Added OptimizationStyle.OptimizeForSimulationSpeed and associated verilator flags to achieve simulation speed.
    • "--x-assign ast" and "--x-initial fast" flags should not really affect behaviour of most Chisel/CIRCT generated code and seem to give some performance boost, but it's open for feedback.
  • added "-j 0" flag to verilator arguments to enable arallelism for uses all available CPU cores for verilate and build jobs
  • added a "ShutdownHook" to kill the simulation process in case of Ctrl+C etc. Tested on macOS only, but seems to be working.

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…ization

- Changed TraceStyle.Vcd to include a trace file name
- Added OptimizationStyle.OptimizeForSimulationSpeed and associated verilator flags
- added a sys.addShutdownHook to kill the simulation process in case of
  Ctrl+C etc. Test on macOS only. Seems to be _mostly_ working, so
probably better than nothing.
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linux-foundation-easycla bot commented Apr 10, 2024

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The committers listed above are authorized under a signed CLA.

@jackkoenig jackkoenig added this to the 7.0 milestone Apr 10, 2024
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LGTM, thanks @kammoh!

@jackkoenig jackkoenig merged commit 263930c into chipsalliance:main Apr 10, 2024
16 of 17 checks passed
SpriteOvO pushed a commit that referenced this pull request Apr 20, 2024
…ization (#3985)

- Changed TraceStyle.Vcd to include a trace file name
- Added OptimizationStyle.OptimizeForSimulationSpeed and associated Verilator flags
- Added a sys.addShutdownHook to kill the simulation process in case of
  Ctrl+C etc. Tested on MacOS only. Seems to be _mostly_ working, so
  probably better than nothing.
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2 participants