How to emit vcd file when using chisel3.simulator for testing?

[longfangsong]

I'm using chisel version 6.2.0, and with the following code:

// TopTest.scala
package test

import Serial.Top
import chisel3._
import chisel3.simulator.EphemeralSimulator._
import org.scalatest.flatspec.AnyFlatSpec

class TopSpec extends AnyFlatSpec {
  behavior of "Top"
  it should "do something" in {
    simulate(new Top) { top =>
        top.clock.step(1)
        top.io.rxWire.poke(true.B)
        top.clock.step(1)
        top.io.rxWire.poke(false.B)
        top.clock.step(1)
    }
  }
}

But I cannot find any vcd file generated when sbt run test, and I cannot find out how to generate it.

Is there anything I am missing?

I guess it is related with #3952?

[hakan-demirli]

I was also looking for an answer and here is what I have found:

Currently it is not possible to dump vcd files without extending the existing simulator. Existing one is EphemeralSimulator object which uses a DefaultSimulator class which extends SingleBackendSimulator with a verilator.Backend.
https://github.com/chipsalliance/chisel/blob/ce05462c239deec8aee0704efbd3a71e8b64ec49/src/main/scala/chisel3/simulator/EphemeralSimulator.scala

In the DefaultSimulator class, the backendSpecificCompilationSettings is set to verilator.Backend.CompilationSettings(), which is the default settings. To enable VCD generation, you would need to modify these settings to include:

traceStyle = Some(CompilationSettings.TraceStyle.Vcd(traceUnderscore = true))

However, the DefaultSimulator class is private and its settings are not exposed for modification. Therefore, you might need to create your own simulator class that extends SingleBackendSimulator and allows you to specify your own backendSpecificCompilationSettings.
Here is an example simulator that can emit vcd file: https://github.com/rameloni/tywaves-chisel-demo/blob/main/src/main/scala/tywaves/simulator/BetterEphemeralSimulator.scala

It is unfortunate that chisel-template is using svsim. Mostly new users use the template and they do not know anything about chisel test frameworks. I also assume most users expect at least a traditional testing framework that supports waveforms. So, offering a half-done simulator with a subpar functionality is doing more bad than good for the adoption of Chisel.

[Emin017]

I also find a demo here: https://github.com/rameloni/tywaves-chisel-demo

[seldridge]

The missing thing is an object like EphemeralSimulator which does actual writes to the disk as opposed to putting everything in temporary directories.

[rameloni]

I recently updated BetterEphemeralSimulator and split it into two new simulators.
It made use of both generic features and also features related to my waveform viewer project.

For general usage you can make use of ParametricSimulator now which doesn't have all the additional information used in the viewer and now works for all circuits supported by svsim https://github.com/rameloni/tywaves-chisel-demo/blob/main/src/main/scala/tywaves/simulator/ParametricSimulator.scala

While TywavesSimulator in the demo now has some issues mainly related to the debug information generation. I'm working on that at the moment.

[edwardcwang]

Adding a solution for vanilla Chisel 6.5 if we want to avoid importing any additional libraries beyond just Chisel.

#4246 (comment)