Fix width of ChiselEnum values in emitted FIRRTL

[jackkoenig]

This is primarily a bug fix, but it changes widths in a way that could silently break user code so I'm framing this as an API Modification that has instructions for users when bumping Chisel. In #3824 we added --use-legacy-shift-right-width to help users migrate to the fixed width semantics for shift-right. I have renamed that option --use-legacy-width and added this width behavior change to the option.

--use-legacy-width is purely a code migration option, this behavior will only be "optionally preserved" for migrating code to Chisel 7, it will be removed in Chisel 8.

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Type of Improvement

• API modification
• Bugfix

Desired Merge Strategy

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Release Notes

Fixes #4159.

Previously, the width reported by Chisel under .getWidth was inconsistent with the width of the emitted FIRRTL for ChiselEnum values cast to UInt.

Temporarily preserve the old behavior under CLI option --use-legacy-width (formerly known as --use-legacy-shift-right-width). Users are encouraged to build Verilog with and without this option enabled and diff the result to verify that this change in width behavior did not silently affect the correctness of their designs.

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