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Fix width of ChiselEnum values in emitted FIRRTL #4200

Merged
merged 2 commits into from
Jul 1, 2024
Merged

Fix width of ChiselEnum values in emitted FIRRTL #4200

merged 2 commits into from
Jul 1, 2024

Commits on Jun 28, 2024

  1. Fix width of ChiselEnum values in emitted FIRRTL 

    Temporarily preserve the old behavior under CLI option
--use-legacy-width (formerly known as --use-legacy-shift-right-width).
Users are encouraged to build Verilog with and without this option
enabled and diff the result to verify that this change in width behavior
did not silently affect the correctness of their designs.
    @jackkoenig
    jackkoenig committed Jun 28, 2024
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  2. Clarify UseLegacyWidthBehavior ScalaDoc

    @jackkoenig
    jackkoenig committed Jun 28, 2024
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