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Update SPIPhysical.scala so channel 0 is sampled in single SPI mode #25

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merged 1 commit into from
Jan 16, 2024

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Kevin99214
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Changed from channel 1 being sampled for single SPI mode

…SPI mode

Changed from channel 1 being sampled for single SPI mode
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linux-foundation-easycla bot commented Jan 15, 2024

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  • ✅ login: Kevin99214 / name: Kevin Qin (20e3631)

@jerryz123
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Can you describe what this PR does a bit more? Is it fixing a bug? Or improving the behavior?

@Kevin99214
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It's a bit of both.

A QSPI model I'm using currently, when set to single SPI mode, responds on channel 0. This then is not being sampled by the device and my SPI reads always return 0.

But intuitively, different modes of SPI samples different amounts of rx input bits.

  • Quad SPI samples all rx bits ([3:0])
  • Dual SPI samples lower 2 indexed rx bits([1:0])
    The next step for Single SPI should be to sample only the lowest index ([0:0]) but it currently samples [1:1]

@jerryz123
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Ok, this change makes sense to me. can you sign the CLA?

@Kevin99214
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Ok signed. Thanks

@jerryz123 jerryz123 merged commit d44f33c into chipsalliance:main Jan 16, 2024
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@T-K-233
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T-K-233 commented Feb 15, 2024

But intuitively, different modes of SPI samples different amounts of rx input bits.

  • Quad SPI samples all rx bits ([3:0])
  • Dual SPI samples lower 2 indexed rx bits([1:0])
    The next step for Single SPI should be to sample only the lowest index ([0:0]) but it currently samples [1:1]

I don't think this pattern is correct for single SPI mode.

Different from Dual and Quad SPI mode, Single SPI mode operates in full-duplex. So there are two pins, MOSI (Master Out Slave In) and MISO (Master In Slave Out).

The convention here is that MOSI gets mapped to pin(0), and MISO mapped to pin(1). Therefore, on receiving in Single SPI mode, it is correct to receive from rxd_fin(1).

Please check if the QSPI model you are using also follows this convention. Could you provide a link to the device you are using?

Thanks.

@Kevin99214
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Ah sorry about that, I just checked the spec again. It does say that pin1 should be the response data pin.

https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf?rev=59de7fdc073c47fd81ff0533f44733ef

Please feel free to revert this change. Thanks

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3 participants