fix: io declaration and explicit import

wrap io declaration and use explicit import Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
chipsalliance · Sep 14, 2022 · 2e7295a · 2e7295a
1 parent c7983d7
commit 2e7295a
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/src/main/scala/groundtest/DummyPTW.scala b/src/main/scala/groundtest/DummyPTW.scala
@@ -4,17 +4,17 @@
 package freechips.rocketchip.groundtest
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.{RRArbiter, Valid, log2Up, RegEnable}
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile.CoreModule
 import freechips.rocketchip.util.ParameterizedBundle
 
 class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
-  val io = new Bundle {
+  val io = IO(new Bundle {
     val requestors = Flipped(Vec(n, new TLBPTWIO))
-  }
+  })
 
   val req_arb = Module(new RRArbiter(Valid(new PTWReq), n))
   req_arb.io.in <> io.requestors.map(_.req)

diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
@@ -20,7 +20,7 @@
 package freechips.rocketchip.groundtest
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.{log2Up, MuxLookup, Cat, log2Ceil, Enum}
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.diplomacy.{ClockCrossingType}
 import freechips.rocketchip.rocket._
@@ -632,4 +632,4 @@ class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp
   status.error.valid := false.B
 
   assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out")
-}
+}