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Merge pull request #2326 from chipsalliance/user-bits-overhall
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User bits overhaul
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@terpstra
terpstra authored Mar 13, 2020
2 parents 1adbf56 + 5c32b2f commit 6f2f91a
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Showing 43 changed files with 740 additions and 805 deletions.
3 changes: 2 additions & 1 deletion src/main/scala/amba/ahb/AHBLite.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,8 @@ class AHBLite()(implicit p: Parameters) extends LazyModule {
out.hprot := in.hprot
out.haddr := in.haddr
out.hwdata := in.hwdata
out.hauser.foreach { _ := in.hauser.get }
out.hauser :<> in.hauser
in.hduser :<> out.hduser
in.hrdata := out.hrdata
}
}
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24 changes: 13 additions & 11 deletions src/main/scala/amba/ahb/Bundles.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,10 @@
package freechips.rocketchip.amba.ahb

import Chisel._
import freechips.rocketchip.util.GenericParameterizedBundle

abstract class AHBBundleBase(params: AHBBundleParameters) extends GenericParameterizedBundle(params)
import freechips.rocketchip.util._

// Signal directions are from the master's point-of-view
class AHBSlaveBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle
{
// Control signals from the arbiter to slave
val hmastlock = Bool(OUTPUT)
Expand All @@ -24,10 +22,11 @@ class AHBSlaveBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
val hburst = UInt(OUTPUT, width = params.burstBits)
val hwrite = Bool(OUTPUT)
val hprot = UInt(OUTPUT, width = params.protBits)
val hauser = if (params.userBits > 0) Some(UInt(OUTPUT, width = params.userBits)) else None
val haddr = UInt(OUTPUT, width = params.addrBits)
val hauser = BundleMap(params.requestFields)

// D-phase signals from arbiter to slave
val hduser = BundleMap(params.responseFields)
val hwdata = UInt(OUTPUT, width = params.dataBits)

// D-phase signals from slave to arbiter
Expand All @@ -42,6 +41,7 @@ class AHBSlaveBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
hrdata.dir match {
case INPUT =>
hreadyout := Bool(false)
hduser :<= BundleMap()
hresp := AHBParameters.RESP_OKAY
hrdata := UInt(0)
case OUTPUT =>
Expand All @@ -53,15 +53,15 @@ class AHBSlaveBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
hburst := AHBParameters.BURST_SINGLE
hwrite := Bool(false)
hprot := AHBParameters.PROT_DEFAULT
hauser.map {_:= UInt(0)}
haddr := UInt(0)
hauser :<= BundleMap()
hwdata := UInt(0)
case _ =>
}
}
}

class AHBMasterBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle
{
// Control signals from master to arbiter
val hmastlock = if (params.lite) Some(Bool(OUTPUT)) else None
Expand All @@ -83,10 +83,11 @@ class AHBMasterBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
val hburst = UInt(OUTPUT, width = params.burstBits)
val hwrite = Bool(OUTPUT)
val hprot = UInt(OUTPUT, width = params.protBits)
val hauser = if (params.userBits > 0) Some(UInt(OUTPUT, width = params.userBits)) else None
val haddr = UInt(OUTPUT, width = params.addrBits)
val hauser = BundleMap(params.requestFields)

// D-phase signals from master to arbiter
val hduser = BundleMap(params.responseFields)
val hwdata = UInt(OUTPUT, width = params.dataBits)

// D-phase response from arbiter to master
Expand All @@ -98,18 +99,19 @@ class AHBMasterBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
case INPUT =>
hgrant.foreach { _ := Bool(false) }
hready := Bool(false)
hduser :<= BundleMap()
hresp := AHBParameters.RESP_OKAY
hrdata := UInt(0)
case OUTPUT =>
lock() := Bool(false)
busreq() := Bool(false)
lock() := Bool(false)
busreq() := Bool(false)
htrans := AHBParameters.TRANS_IDLE
hsize := UInt(0)
hburst := AHBParameters.BURST_SINGLE
hwrite := Bool(false)
hprot := AHBParameters.PROT_DEFAULT
hauser.map {_:= UInt(0)}
haddr := UInt(0)
hauser :<= BundleMap()
hwdata := UInt(0)
case _ =>
}
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39 changes: 21 additions & 18 deletions src/main/scala/amba/ahb/Parameters.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import scala.math.{max, min}

case class AHBSlaveParameters(
Expand Down Expand Up @@ -41,9 +42,11 @@ case class AHBSlaveParameters(
}

case class AHBSlavePortParameters(
slaves: Seq[AHBSlaveParameters],
beatBytes: Int,
lite: Boolean)
slaves: Seq[AHBSlaveParameters],
beatBytes: Int,
lite: Boolean,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil)
{
require (!slaves.isEmpty)
require (isPow2(beatBytes))
Expand All @@ -67,21 +70,19 @@ case class AHBSlavePortParameters(

case class AHBMasterParameters(
name: String,
nodePath: Seq[BaseNode] = Seq(),
userBits: Seq[UserBits] = Nil){
val userBitsWidth = userBits.map(_.width).sum
}
nodePath: Seq[BaseNode] = Nil)

case class AHBMasterPortParameters(
masters: Seq[AHBMasterParameters]){
val userBitsWidth = masters.map(_.userBitsWidth).max
}
masters: Seq[AHBMasterParameters],
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil)

case class AHBBundleParameters(
addrBits: Int,
dataBits: Int,
userBits: Int,
lite: Boolean)
addrBits: Int,
dataBits: Int,
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
lite: Boolean)
{
require (dataBits >= 8)
require (addrBits >= 1)
Expand All @@ -99,23 +100,25 @@ case class AHBBundleParameters(
AHBBundleParameters(
max(addrBits, x.addrBits),
max(dataBits, x.dataBits),
userBits,
BundleField.union(requestFields ++ x.requestFields),
BundleField.union(responseFields ++ x.responseFields),
lite)
}
}

object AHBBundleParameters
{
val emptyBundleParams = AHBBundleParameters(addrBits = 1, dataBits = 8, userBits = 0, lite = true)
val emptyBundleParams = AHBBundleParameters(addrBits = 1, dataBits = 8, requestFields = Nil, responseFields = Nil, lite = true)
def union(x: Seq[AHBBundleParameters]) =
if (x.isEmpty) emptyBundleParams else x.tail.foldLeft(x.head)((x,y) => x.union(y))

def apply(master: AHBMasterPortParameters, slave: AHBSlavePortParameters) =
new AHBBundleParameters(
addrBits = log2Up(slave.maxAddress+1),
dataBits = slave.beatBytes * 8,
userBits = master.userBitsWidth,
lite = slave.lite)
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
lite = slave.lite)
}

case class AHBEdgeParameters(
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5 changes: 2 additions & 3 deletions src/main/scala/amba/ahb/RegisterRouter.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
import freechips.rocketchip.util.{HeterogeneousBag, MaskGen}
import freechips.rocketchip.util._
import scala.math.{min,max}

case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
Expand All @@ -28,7 +28,7 @@ case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes:
val (ahb, _) = this.in(0)

val indexBits = log2Up((address.mask+1)/beatBytes)
val params = RegMapperParams(indexBits, beatBytes, 1)
val params = RegMapperParams(indexBits, beatBytes)
val in = Wire(Decoupled(new RegMapperInput(params)))
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)

Expand All @@ -46,7 +46,6 @@ case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes:
in.bits.index := d_index
in.bits.data := ahb.hwdata
in.bits.mask := d_mask
in.bits.extra := UInt(0)

when (ahb.hready) { d_phase := Bool(false) }
ahb.hreadyout := !d_phase || out.valid
Expand Down
40 changes: 29 additions & 11 deletions src/main/scala/amba/ahb/ToTL.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,20 +3,24 @@
package freechips.rocketchip.amba.ahb

import Chisel._
import freechips.rocketchip.amba._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.MaskGen
import freechips.rocketchip.util._

case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImpSlave, TLImp)(
dFn = { case AHBMasterPortParameters(masters) =>
TLClientPortParameters(clients = masters.map { m =>
// AHB fixed length transfer size maximum is 16384 = 1024 * 16 bits, hsize is capped at 111 = 1024 bit transfer size and hburst is capped at 111 = 16 beat burst
// This master can only produce:
// emitsGet = TransferSizes(1, 2048),
// emitsPutFull = TransferSizes(1, 2048)
TLClientParameters(name = m.name, nodePath = m.nodePath)
})
dFn = { case mp =>
TLClientPortParameters(
clients = mp.masters.map { m =>
// AHB fixed length transfer size maximum is 16384 = 1024 * 16 bits, hsize is capped at 111 = 1024 bit transfer size and hburst is capped at 111 = 16 beat burst
// This master can only produce:
// emitsGet = TransferSizes(1, 2048),
// emitsPutFull = TransferSizes(1, 2048)
TLClientParameters(name = m.name, nodePath = m.nodePath)
},
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys)
},
uFn = { mp => AHBSlavePortParameters(
slaves = mp.managers.map { m =>
Expand All @@ -36,8 +40,10 @@ case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHB
nodePath = m.nodePath,
supportsWrite = adjust(m.supportsPutFull),
supportsRead = adjust(m.supportsGet))},
beatBytes = mp.beatBytes,
lite = true)
beatBytes = mp.beatBytes,
lite = true,
responseFields = mp.responseFields,
requestKeys = mp.requestKeys.filter(_ != AMBAProt))
})

class AHBToTL()(implicit p: Parameters) extends LazyModule
Expand All @@ -55,6 +61,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
val d_write = RegInit(Bool(false))
val d_addr = Reg(in.haddr)
val d_size = Reg(out.a.bits.size)
val d_user = Reg(BundleMap(edgeOut.bundle.requestFields))

when (out.d.valid) { d_recv := Bool(false) }
when (out.a.ready) { d_send := Bool(false) }
Expand Down Expand Up @@ -98,6 +105,15 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
d_write := in.hwrite
d_addr := in.haddr
d_size := Mux(a_burst_ok, a_burst_size, in.hsize)
d_user :<= in.hauser
d_user.lift(AMBAProt).foreach { x =>
x.fetch := !in.hprot(0)
x.privileged := in.hprot(1)
x.bufferable := in.hprot(2)
x.cacheable := in.hprot(3)
x.secure := false.B
x.modifiable := in.hprot(3)
}
}
}

Expand All @@ -110,6 +126,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
out.a.bits.data := in.hwdata
out.a.bits.mask := MaskGen(d_addr, d_size, beatBytes)
out.a.bits.corrupt := Bool(false)
out.a.bits.user :<= d_user

out.d.ready := d_recv // backpressure AccessAckData arriving faster than AHB beats

Expand All @@ -120,6 +137,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
// response. ERROR responses do not require valid read data."
// Therefore, we choose to accept this slight TL-AHB infidelity.
in.hrdata := out.d.bits.data
in.hduser :<= out.d.bits.user

// In a perfect world, we'd use these signals
val hresp = d_fail || (out.d.valid && (out.d.bits.denied || out.d.bits.corrupt))
Expand Down
13 changes: 10 additions & 3 deletions src/main/scala/amba/ahb/Xbar.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -6,12 +6,18 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.util._
import scala.math.{min,max}

class AHBFanout()(implicit p: Parameters) extends LazyModule {
val node = AHBFanoutNode(
masterFn = { case Seq(m) => m },
slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
slaveFn = { seq =>
seq(0).copy(
slaves = seq.flatMap(_.slaves),
requestKeys = seq.flatMap(_.requestKeys).distinct,
responseFields = BundleField.union(seq.flatMap(_.responseFields)))
})

lazy val module = new LazyModuleImp(this) {
if (node.edges.in.size >= 1) {
Expand All @@ -38,7 +44,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {

when (in.hready) { d_sel := a_sel }
(a_sel zip io_out) foreach { case (sel, out) =>
out := in
out :<> in
out.hsel := in.hsel && sel
out.hmaster.map { _ := UInt(0) }
}
Expand Down Expand Up @@ -77,8 +83,9 @@ class AHBArbiter()(implicit p: Parameters) extends LazyModule {
in.hrdata := out.hrdata
in.hresp := out.hresp // zero-extended
in.hgrant.foreach { _ := Bool(true) }
out.hauser.foreach { _ := in.hauser.get }
out.hmaster.foreach { _ := UInt(0) }
out.hauser :<= in.hauser
in.hduser :<= out.hduser
}
}
}
12 changes: 6 additions & 6 deletions src/main/scala/amba/apb/Bundles.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,10 @@
package freechips.rocketchip.amba.apb

import Chisel._
import freechips.rocketchip.util.GenericParameterizedBundle

abstract class APBBundleBase(params: APBBundleParameters) extends GenericParameterizedBundle(params)
import freechips.rocketchip.util._

// Signal directions are from the master's point-of-view
class APBBundle(params: APBBundleParameters) extends APBBundleBase(params)
class APBBundle(val params: APBBundleParameters) extends Bundle
{
// Flow control signals from the master
val psel = Bool(OUTPUT)
Expand All @@ -20,25 +18,27 @@ class APBBundle(params: APBBundleParameters) extends APBBundleBase(params)
val pprot = UInt(OUTPUT, width = params.protBits)
val pwdata = UInt(OUTPUT, width = params.dataBits)
val pstrb = UInt(OUTPUT, width = params.dataBits/8)
val pauser = if (params.userBits > 0) Some(UInt(OUTPUT, width = params.userBits)) else None
val pauser = BundleMap(params.requestFields)

val pready = Bool(INPUT)
val pslverr = Bool(INPUT)
val prdata = UInt(INPUT, width = params.dataBits)
val pduser = BundleMap(params.responseFields)

def tieoff() {
pready.dir match {
case INPUT =>
pready := Bool(false)
pslverr := Bool(false)
prdata := UInt(0)
pduser :<= BundleMap()
case OUTPUT =>
pwrite := Bool(false)
paddr := UInt(0)
pprot := APBParameters.PROT_DEFAULT
pwdata := UInt(0)
pstrb := UInt(0)
pauser.map {_ := UInt(0)}
pauser :<= BundleMap()
case _ =>
}
}
Expand Down
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