fix Chisel compile warnings in PseudoLRU.access(ways: Seq) (#2378)

chipsalliance · Apr 4, 2020 · 8e1f0c8 · 8e1f0c8
1 parent 2cef6e4
commit 8e1f0c8
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/src/main/scala/util/Replacement.scala b/src/main/scala/util/Replacement.scala
@@ -44,8 +44,7 @@ class PseudoLRU(n: Int)
     state_reg := get_next_state(state_reg,way)
   }
   def access(ways: Seq[ValidIO[UInt]]) {
-    state_reg := ways.fold(state_reg) { case (prev: UInt, way: ValidIO[UInt]) =>
-      Mux(way.valid, get_next_state(prev, way.bits), prev) }
+    state_reg := ways.foldLeft(state_reg)((prev, way) => Mux(way.valid, get_next_state(prev, way.bits), prev))
   }
   def get_next_state(state: UInt, way: UInt) = {
     var next_state = state << 1