fix Chisel compile warnings in PseudoLRU.access(ways: Seq)

[ingallsj]

Related issue: introduced by me in 9057b3c
Type of change: other enhancement (paying off technical debt)
Impact: no functional change
Development Phase: implementation

fix these Chisel compile warnings:

[warn] /rocket-chip/src/main/scala/util/Replacement.scala:46:39: match may not be exhaustive.
[warn] It would fail on the following inputs: (UInt(), _), (_, Valid()), (_, _)
[warn]     state_reg := ways.fold(state_reg) { case (prev: UInt, way: ValidIO[UInt]) =>
[warn]                                       ^
[warn] /rocket-chip/src/main/scala/util/Replacement.scala:46:64: non-variable type argument Chisel.UInt in type pattern chisel3.util.Valid[Chisel.UInt] (the underlying of Chisel.ValidIO[Chisel.UInt]) is unchecked since it is eliminated by erasure
[warn]     state_reg := ways.fold(state_reg) { case (prev: UInt, way: ValidIO[UInt]) =>
[warn]                                                                ^

[aswaterman]

The intent of the original code is clearer.

The match is only necessary because of the use of fold rather than foldLeft, but I think foldLeft is preferable anyway: we aren't trying to imply that different elaborations might produce different orderings. Try this instead:

def access(ways: Seq[ValidIO[UInt]]) {
  state_reg := ways.foldLeft(state_reg)((prev, way) => Mux(way.valid, get_next_state(prev, way.bits), prev))
}

[ingallsj]

that seems to work, thank you for the magic incantation!