PLRU: multiple access update

chipsalliance · Feb 4, 2020 · 9057b3c · 9057b3c
1 parent 36d87ef
commit 9057b3c
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/src/main/scala/util/Replacement.scala b/src/main/scala/util/Replacement.scala
@@ -42,6 +42,10 @@ class PseudoLRU(n: Int)
   def access(way: UInt) {
     state_reg := get_next_state(state_reg,way)
   }
+  def access(ways: Seq[ValidIO[UInt]]) {
+    state_reg := ways.fold(state_reg) { case (prev: UInt, way: ValidIO[UInt]) =>
+      Mux(way.valid, get_next_state(prev, way.bits), prev) }
+  }
   def get_next_state(state: UInt, way: UInt) = {
     var next_state = state << 1
     var idx = UInt(1,1)