Merge pull request #2420 from chipsalliance/cease-assertion

Add assertion on CEASE line
chipsalliance · Apr 27, 2020 · e1a5b25 · e1a5b25
2 parents 8acb224 + 2c9e91b
commit e1a5b25
Showing 1 changed file with 7 additions and 1 deletion.
diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala
@@ -102,7 +102,13 @@ trait SourcesExternalNotifications { this: BaseTile =>
       saturated
     }
     val (cease, _) = ceaseNode.out(0)
-    cease(0) := could_cease.map(waitForQuiescence(_)).getOrElse(false.B)
+    cease(0) := could_cease.map{ c => 
+      val cease = (waitForQuiescence(c))
+      // Test-Only Code --
+      val prev_cease = RegNext(c, false.B)
+      assert(!(prev_cease & !c), "CEASE line can not glitch once raised") 
+      cease
+    }.getOrElse(false.B)
   }
 
   // Report when the tile is waiting for an interrupt