PRCI: use RecordMap API to get easier to follow names on clock group signals

[mwachs5]

Related issue:

Redo of #2487 which seems to have rebase issues
Bumps FIRRTL along 1.3.x

This builds on top of #2486 and will be rebased on top of it as that API changes.

This demonstrates the use of the new RecordMap. API to get better names for clock group signals

In the comments I'll include a diff before and after this change.

Type of change:feature request

Impact: API modification

(Generated RTL will have different output)
Also bumps firrtl along 1.3.x branch which notably changes the Dedup behavior (this was a bug before)

Development Phase: implementation

Release Notes

I/O and internal signals in the clock related modules (ClockSource, ClockGroup, etc) will have more meaningful I/O names vs simply indexed names. This also results in less deduplication of ClockGroup-related modules as their names are different.

Firrtl Bump Notes

Feature

• Constant propagate reduction operators (Constant Prop Reduction Operations of Literals firrtl#1558)
• Add find_heap_bound.py (Find Heap Bound firrtl#1648)
• Squash skips and nested blocks in Block.mapStmt (Find Heap Bound firrtl#1648)

Bugfix

• Improved source locators when using append info (Have AppendInfo use MultiInfo, rather than appending with : firrtl#1580)
• Fix some missing transform invalidations (Add Some Missing Invalidations firrtl#1541)
• Fix handling of non-reset registers in RemoveReset (Canonicalize init of regs with zero as reset in RemoveReset firrtl#1627)
• Don't dedup main module (Don't try deduping the main module of a circuit firrtl#1594)
• Don't crash on -ll trace when annotations aren't serializable (Improve anno logging firrtl#1639)
• Fix stack overflows in CheckWidths (Limit recursion (and reduce total work) in CheckWidths firrtl#1646)
  • Also performance improvement for some designs
• Remove non-determinism in transform ordering (delete usages of toSet for determinism firrtl#1686)
• Restore 1.2.x meaning of -X high in CLI (Set prerequisite of -X high to MinimalHighForm firrtl#1704)
• Add support for ValidIf to ProtoBuf [de]serialization (Add support for ValidIf to ProtoBuf [de]serialization firrtl#1707)
• Don't Dedup modules if it would break connection semantics (Don't Dedup modules if it would change semantics firrtl#1713)

Performance

• Speed up InferTypes and CInferTypes (Speed up InferTypes and CInferTypes firrtl#1601)
• Speed up Deduplication (Speed up Deduplication firrtl#1602)
• Speed up ResolveKinds (Add basic transform benchmarking infrastructure and speed up Resolve Kinds firrtl#1475)
• Speed up ExpandWhens for some very large designs (Speed up ExpandWhens for very large designs firrtl#1666)

[mwachs5]

blocked by chipsalliance/firrtl#1703

[jackkoenig]

Firrtl Bump Notes

Feature

• Constant propagate reduction operators (Constant Prop Reduction Operations of Literals firrtl#1558)
• Emit wire assignments inline with declaration (consolidated wire+assign to just wire, with expression inlined firrtl#1600)
• Add find_heap_bound.py (Find Heap Bound firrtl#1648)
• Squash skips and nested blocks in Block.mapStmt (Find Heap Bound firrtl#1648)

Bugfix

• Improved source locators when using append info (Have AppendInfo use MultiInfo, rather than appending with : firrtl#1580)
• Fix some missing transform invalidations (Add Some Missing Invalidations firrtl#1541)
• Fix handling of non-reset registers in RemoveReset (Canonicalize init of regs with zero as reset in RemoveReset firrtl#1627)
• Don't dedup main module (Don't try deduping the main module of a circuit firrtl#1594)
• Don't crash on -ll trace when annotations aren't serializable (Improve anno logging firrtl#1639)
• Fix stack overflows in CheckWidths (Limit recursion (and reduce total work) in CheckWidths firrtl#1646)
  • Also performance improvement for some designs
• Remove non-determinism in transform ordering (delete usages of toSet for determinism firrtl#1686)
• Restore 1.2.x meaning of -X high in CLI (Set prerequisite of -X high to MinimalHighForm firrtl#1704)
• Add support for ValidIf to ProtoBuf [de]serialization (Add support for ValidIf to ProtoBuf [de]serialization firrtl#1707)
• Don't Dedup modules if it would break connection semantics (Don't Dedup modules if it would change semantics firrtl#1713)

Performance

• Speed up InferTypes and CInferTypes (Speed up InferTypes and CInferTypes firrtl#1601)
• Speed up Deduplication (Speed up Deduplication firrtl#1602)
• Speed up ResolveKinds (Add basic transform benchmarking infrastructure and speed up Resolve Kinds firrtl#1475)
• Speed up ExpandWhens for some very large designs (Speed up ExpandWhens for very large designs firrtl#1666)

[mwachs5]

@hcook can I get an approval on this?
(or @jackkoenig ?)

[jackkoenig]

LGTM