Add 'tests/shouldfail/Cores/' from commit '4a6a82ab88b43de7e1b2639d3b…

…c42f0e5788589c'

git-subtree-dir: tests/shouldfail/Cores
git-subtree-mainline: e205083
git-subtree-split: 4a6a82a

tests/shouldfail/Cores/Xilinx/VIO/DuplicateInputNames.hs

@@ -0,0 +1,15 @@
+module DuplicateInputNames where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = "a" :> "a" :> Nil
+outNames = "b" :> Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "in" ::: Signal Dom (Bit, Bit) ->
+  "out" ::: Signal Dom Bit
+topEntity = vioProbe @Dom inNames outNames 0

tests/shouldfail/Cores/Xilinx/VIO/DuplicateInputOutputNames.hs

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+module DuplicateInputOutputNames where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = "a" :> Nil
+outNames = "a" :> Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "in" ::: Signal Dom Bit ->
+  "out" ::: Signal Dom Bit
+topEntity = vioProbe @Dom inNames outNames 0

tests/shouldfail/Cores/Xilinx/VIO/DuplicateOutputNames.hs

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+module DuplicateOutputNames where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = Nil
+outNames = "a" :> "a" :> Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "out" ::: Signal Dom (Bit, Bit)
+topEntity = vioProbe @Dom inNames outNames (0, 0)

tests/shouldfail/Cores/Xilinx/VIO/InputBusWidthExceeded.hs

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+module InputBusWidthExceeded where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = singleton "probe_in"
+outNames = Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "in"  ::: Signal Dom (BitVector 257) ->
+  "out" ::: Signal Dom ()
+topEntity = vioProbe @Dom inNames outNames ()

tests/shouldfail/Cores/Xilinx/VIO/InputProbesExceeded.hs

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+module InputProbesExceeded where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+import qualified Data.List as L
+
+type Dom = XilinxSystem
+
+inNames = $(listToVecTH (L.map (("probe_in_" <>) . show) [0::Int, 1..256]))
+outNames = Nil
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "in"  ::: Signal Dom (Vec 257 Bool) ->
+  "out" ::: Signal Dom ()
+topEntity = vioProbe @Dom inNames outNames ()

tests/shouldfail/Cores/Xilinx/VIO/OutputBusWidthExceeded.hs

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+module OutputBusWidthExceeded where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+type Dom = XilinxSystem
+
+inNames = Nil
+outNames = singleton "probe_out"
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "out" ::: Signal Dom (BitVector 257)
+topEntity = vioProbe @Dom inNames outNames 0

tests/shouldfail/Cores/Xilinx/VIO/OutputProbesExceeded.hs

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+module OutputProbesExceeded where
+
+import Clash.Prelude
+import Clash.Cores.Xilinx.VIO
+
+import qualified Data.List as L
+
+type Dom = XilinxSystem
+
+inNames = Nil
+outNames = $(listToVecTH (L.map (("probe_out_" <>) . show) [0::Int, 1..256]))
+
+topEntity ::
+  "clk" ::: Clock Dom ->
+  "out" ::: Signal Dom (Vec 257 Bit)
+topEntity = vioProbe @Dom inNames outNames (replicate (SNat @257) low)