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Enable multi-register intrinsics support for Arm64 #64921
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Tagging subscribers to this area: @JulieLeeMSFT Issue DetailsOverviewWe achieved parity with x64 for Arm64 intrinsics support in .NET 5 for most of them except for multi-register intrinsics. We need more work to enable multi-register intrinsics for Arm64. The work is integral in that it involves changes in JIT, libraries and mono to enable working intrinsics. Work Items
Follow-up (after the JIT work is completed)
Benchmarks to use
|
will it fix |
Not this work item, which I tend to think of as "LSRA allocating spans of registers" work. However #64864 should lay foundation for |
Moved to .NET 8. |
We will continue working on #84510 in .NET 9. |
This is completed. |
Overview
We achieved parity with x64 for Arm64 intrinsics support in .NET 5 for most of them except for multi-register intrinsics. We need more work to enable multi-register intrinsics for Arm64. The work is integral in that it involves changes in JIT, libraries and mono to enable working intrinsics.
Work Items
LoadPairVector64/128
in the libraries (see comment)V0-V2
(note that this is different from theLoadPairVector64/128
which returns result in two independent SIMD registers). [LSRA] Add support for allocating consecutive registers #39457. Implemented in Arm64: Implement VectorTableLookup/VectorTableLookupExtension intrinsinsic + Consecutive registers support #80297.LoadVector
andStoreVector
APIs on Arm64 ([API Proposal]: Arm64 [Load/Store]Vector64 and [Load/Store]Vector128 for 2,3 and 4 variants #84510)LoadVector
andStoreVector
APIs on Arm64 (such as ones that will exposeLD[1-4]
,ST[1-4]
instructions)TBL
,TBX
instructions)Follow-up (after the JIT work is completed)
Benchmarks to use
category:cq
theme:register-allocator
skill-level:expert
cost:medium
impact:medium
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