Couple optimization to MultiRegStoreLoc #64857

echesakov · 2022-02-05T22:25:29Z

The diffs are net positive. There are some regressions. Looked at couple of them - do not see how they can be mitigated - they are due to re-shuffling of the registers in LSRA.

Here is a description of the change:

Preference the source registers to the destination of multi-register GT_STORE_LCL_VAR if the source is last-use local or not a local (i.e. a multi-reg call or hardware intrinsic). The similar strategy is already done for single reg GT_STORE_LCL_VAR.
Properly check for the last use of a field of a multi-reg local in LinearScan::BuildStoreLocDef().
The second issue can be demonstrated by examples.

Consider the following program:

using System;
using System.Runtime.CompilerServices;

namespace Runtime_64857
{
    class Program
    {
        struct int64x2
        {
            public ulong _0;
            public ulong _1;
        }

        [MethodImpl(MethodImplOptions.NoInlining)]
        static int64x2 Def()
        {
            return default(int64x2);
        }

        [MethodImpl(MethodImplOptions.NoInlining)]
        static void Use(ulong x0, ulong x1)
        {
        }

        static void Main(string[] args)
        {
            var val = Def();
            Use(val._0, val._0);
        }
    }
}

The code diffs for Main (on win-arm64):

diff --git a/base.txt b/diff.txt
index d080ead..b5176ec 100644
--- a/base.txt
+++ b/diff.txt
@@ -11,34 +11,31 @@
 ;# V02 OutArgs      [V02    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   "OutgoingArgSpace"
 ;* V03 tmp1         [V03    ] (  0,  0   )  struct (16) zero-ref    do-not-enreg[SBR] multireg-ret "Return value temp for multireg return"
 ;  V04 tmp2         [V04,T00] (  3,  3   )    long  ->   x0         V01._0(offs=0x00) P-INDEP "field V01._0 (fldOffset=0x0)"
-;  V05 tmp3         [V05,T01] (  1,  1   )    long  ->  x19         V01._1(offs=0x08) P-INDEP "field V01._1 (fldOffset=0x8)"
+;  V05 tmp3         [V05,T01] (  1,  1   )    long  ->   x1         V01._1(offs=0x08) P-INDEP "field V01._1 (fldOffset=0x8)"
 ;* V06 tmp4         [V06    ] (  0,  0   )    long  ->  zero-ref    V03._0(offs=0x00) P-DEP "field V03._0 (fldOffset=0x0)"
 ;* V07 tmp5         [V07    ] (  0,  0   )    long  ->  zero-ref    V03._1(offs=0x08) P-DEP "field V03._1 (fldOffset=0x8)"
 ;
-; Lcl frame size = 8
+; Lcl frame size = 0
 
 G_M3731_IG01:              ;; offset=0000H
-        A9BE7BFD          stp     fp, lr, [sp,#-32]!
-        F9000FF3          str     x19, [sp,#24]
+        A9BF7BFD          stp     fp, lr, [sp,#-16]!
         910003FD          mov     fp, sp
-						;; bbWeight=1    PerfScore 2.50
-G_M3731_IG02:              ;; offset=000CH
+						;; bbWeight=1    PerfScore 1.50
+G_M3731_IG02:              ;; offset=0008H
         94000000          bl      Runtime_64857.Program:Def():int64x2
-        AA0103F3          mov     x19, x1
         AA0003E1          mov     x1, x0
         94000000          bl      Runtime_64857.Program:Use(long,long)
-						;; bbWeight=1    PerfScore 3.00
-G_M3731_IG03:              ;; offset=001CH
-        F9400FF3          ldr     x19, [sp,#24]
-        A8C27BFD          ldp     fp, lr, [sp],#32
+						;; bbWeight=1    PerfScore 2.50
+G_M3731_IG03:              ;; offset=0014H
+        A8C17BFD          ldp     fp, lr, [sp],#16
         D65F03C0          ret     lr
-						;; bbWeight=1    PerfScore 4.00
+						;; bbWeight=1    PerfScore 2.00
 
-; Total bytes of code 40, prolog size 12, PerfScore 13.50, instruction count 10, allocated bytes for code 40 (MethodHash=8297f16c) for method Runtime_64857.Program:Main(System.String[])
+; Total bytes of code 28, prolog size 8, PerfScore 8.80, instruction count 7, allocated bytes for code 28 (MethodHash=8297f16c) for method Runtime_64857.Program:Main(System.String[])

Note that in the base case a variable that corresponds to promoted val._1 was added (unnecessarily) to currentLiveVars and, as a consequence, x19 was used to keep a dead value of the variable.

Now, if you consider another program:

using System;
using System.Runtime.CompilerServices;

namespace Runtime_64857
{
    class Program
    {
        struct int64x2
        {
            public ulong _0;
            public ulong _1;
        }

        [MethodImpl(MethodImplOptions.NoInlining)]
        static int64x2 Def()
        {
            return default(int64x2);
        }

        [MethodImpl(MethodImplOptions.NoInlining)]
        static void TrashRegs()
        {
        }

        [MethodImpl(MethodImplOptions.NoInlining)]
        static void Use(ulong x0, ulong x1)
        {
        }

        static void Main(string[] args)
        {
            var val = Def();
            TrashRegs();
            Use(val._1, val._1);
        }
    }
}

the diffs are opposite in some sense

diff --git a/base.txt b/diff.txt
index c3b5ab8..181e57b 100644
--- a/base.txt
+++ b/diff.txt
@@ -11,34 +11,36 @@
 ;# V02 OutArgs      [V02    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   "OutgoingArgSpace"
 ;* V03 tmp1         [V03    ] (  0,  0   )  struct (16) zero-ref    do-not-enreg[SBR] multireg-ret "Return value temp for multireg return"
 ;  V04 tmp2         [V04,T01] (  1,  1   )    long  ->   x0         V01._0(offs=0x00) P-INDEP "field V01._0 (fldOffset=0x0)"
-;  V05 tmp3         [V05,T00] (  3,  3   )    long  ->  [fp+18H]   V01._1(offs=0x08) P-INDEP "field V01._1 (fldOffset=0x8)"
+;  V05 tmp3         [V05,T00] (  3,  3   )    long  ->  x19         V01._1(offs=0x08) P-INDEP "field V01._1 (fldOffset=0x8)"
 ;* V06 tmp4         [V06    ] (  0,  0   )    long  ->  zero-ref    V03._0(offs=0x00) P-DEP "field V03._0 (fldOffset=0x0)"
 ;* V07 tmp5         [V07    ] (  0,  0   )    long  ->  zero-ref    V03._1(offs=0x08) P-DEP "field V03._1 (fldOffset=0x8)"
 ;
-; Lcl frame size = 16
+; Lcl frame size = 8
 
 G_M3731_IG01:              ;; offset=0000H
         A9BE7BFD          stp     fp, lr, [sp,#-32]!
+        F9000FF3          str     x19, [sp,#24]
         910003FD          mov     fp, sp
-						;; bbWeight=1    PerfScore 1.50
-G_M3731_IG02:              ;; offset=0008H
+						;; bbWeight=1    PerfScore 2.50
+G_M3731_IG02:              ;; offset=000CH
         94000000          bl      Runtime_64857.Program:Def():int64x2
-        F9000FA1          str     x1, [fp,#24]
+        AA0103F3          mov     x19, x1
         94000000          bl      Runtime_64857.Program:TrashRegs()
-        F9400FA0          ldr     x0, [fp,#24]	// [V05 tmp3]
-        AA0003E1          mov     x1, x0
+        AA1303E0          mov     x0, x19
+        AA1303E1          mov     x1, x19
         94000000          bl      Runtime_64857.Program:Use(long,long)
-						;; bbWeight=1    PerfScore 6.50
-G_M3731_IG03:              ;; offset=0020H
+						;; bbWeight=1    PerfScore 4.50
+G_M3731_IG03:              ;; offset=0024H
+        F9400FF3          ldr     x19, [sp,#24]
         A8C27BFD          ldp     fp, lr, [sp],#32
         D65F03C0          ret     lr
-						;; bbWeight=1    PerfScore 2.00
+						;; bbWeight=1    PerfScore 4.00
 
-; Total bytes of code 40, prolog size 8, PerfScore 14.00, instruction count 10, allocated bytes for code 40 (MethodHash=8297f16c) for method Runtime_64857.Program:Main(System.String[])
+; Total bytes of code 48, prolog size 12, PerfScore 15.80, instruction count 12, allocated bytes for code 48 (MethodHash=8297f16c) for method Runtime_64857.Program:Main(System.String[])

val._1 was NOT added to currentLiveVars and instead of assigning a callee-saved register to val._1 (to be able to survive a call to TrashRegs()) the value had to be spilled on the stack.

echesakov · 2022-02-06T00:52:11Z

/azp run runtime-coreclr outerloop

azure-pipelines · 2022-02-06T00:55:54Z

Azure Pipelines successfully started running 1 pipeline(s).

ghost · 2022-02-06T01:09:32Z

Tagging subscribers to this area: @JulieLeeMSFT
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Issue Details

null

Author:	echesakovMSFT
Assignees:	echesakovMSFT
Labels:	`area-CodeGen-coreclr`
Milestone:	-

echesakov · 2022-02-07T20:34:10Z

/azp run runtime-coreclr outerloop

…ters as src in src/coreclr/jit/lsrabuild.cpp

…nearScan::BuildStoreLocDef() in src/coreclr/jit/lsrabuild.cpp

echesakov · 2022-02-15T01:36:43Z

@dotnet/jit-contrib PTAL

kunalspathak · 2022-02-15T01:53:34Z

/azp run runtime-coreclr jitstressregs

azure-pipelines · 2022-02-15T01:53:49Z

Azure Pipelines successfully started running 1 pipeline(s).

kunalspathak

LGTM as long as jitstressregs is clean.

echesakov · 2022-02-15T17:35:16Z

LGTM as long as jitstressregs is clean.

Taking a look at the linux-arm failures.

echesakov · 2022-02-15T20:03:20Z

The failures on linux-arm are known #65395 and macos-x64 ones look like an infrastructure hiccup.
I could try to re-trigger them.

echesakov · 2022-02-15T23:32:56Z

macos-x64 is clean after re-run (https://dev.azure.com/dnceng/public/_build/results?buildId=1612824&view=logs&j=4621ec7e-3d9b-5fdb-df5a-cf7177b660c1)

EgorBo · 2022-02-17T16:34:43Z

Improvements on arm64: dotnet/perf-autofiling-issues#3565

Change dotnet#64857 exposed an existing problem where when generating code for a multi-reg GT_STORE_LCL_VAR, if the first register slot was not enregistered, but the second or subsequent slots was, and those non-first slots contained GC pointers, we wouldn't properly add those GC pointers to the GC tracking sets. This led to cases where the register lifetimes would be killed in the GC info before the actual lifetime was complete. The primary fix is to make `gtHasReg()` handle the `IsMultiRegLclVar()` case. As a side-effect, this fixes some LSRA dumps that weren't displaying multiple registers properly. There are about 50 SPMI asm diffs on win-arm64 where register lifetimes get extended, fixing GC holes. I also made `GetMultiRegCount()` handle the `IsMultiRegLclVar()` case. I made a number of cleanup changes along the way: 1. Fixed two cases of calling `gcInfo.gcMarkRegSetNpt` with regNumber, not regMaskTP 2. Marked some functions `const` 3. Improved some comments 4. Changed "ith" to "i'th" in comments which still doesn't read great, but at least I'm not left trying to parse "ith" as an English word. 5. Use `OperIsScalarLocal()` more broadly 6. Renamed `gtDispRegCount` to `gtDispMultiRegCount` to make it clear it only applies to the multi-reg case. Fixes dotnet#65476.

* Fix GC hole with multi-reg local var stores Change #64857 exposed an existing problem where when generating code for a multi-reg GT_STORE_LCL_VAR, if the first register slot was not enregistered, but the second or subsequent slots was, and those non-first slots contained GC pointers, we wouldn't properly add those GC pointers to the GC tracking sets. This led to cases where the register lifetimes would be killed in the GC info before the actual lifetime was complete. The primary fix is to make `gtHasReg()` handle the `IsMultiRegLclVar()` case. As a side-effect, this fixes some LSRA dumps that weren't displaying multiple registers properly. There are about 50 SPMI asm diffs on win-arm64 where register lifetimes get extended, fixing GC holes. I also made `GetMultiRegCount()` handle the `IsMultiRegLclVar()` case. I made a number of cleanup changes along the way: 1. Fixed two cases of calling `gcInfo.gcMarkRegSetNpt` with regNumber, not regMaskTP 2. Marked some functions `const` 3. Improved some comments 4. Changed "ith" to "i'th" in comments which still doesn't read great, but at least I'm not left trying to parse "ith" as an English word. 5. Use `OperIsScalarLocal()` more broadly 6. Renamed `gtDispRegCount` to `gtDispMultiRegCount` to make it clear it only applies to the multi-reg case. Fixes #65476. * Update src/coreclr/jit/gentree.cpp Co-authored-by: Kunal Pathak <Kunal.Pathak@microsoft.com> Co-authored-by: Kunal Pathak <Kunal.Pathak@microsoft.com>

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 5, 2022

echesakov closed this Feb 6, 2022

echesakov reopened this Feb 6, 2022

ghost assigned echesakov Feb 6, 2022

echesakov closed this Feb 7, 2022

echesakov reopened this Feb 7, 2022

This was referenced Feb 7, 2022

Enable multi-register intrinsics support for Arm64 #64921

Closed

Implement LoadPairVector64 and LoadPairVector128 #64864

Merged

echesakov added 2 commits February 10, 2022 08:05

For StoreLoc prefer allocating a multireg local def in the same regis…

cc874c5

…ters as src in src/coreclr/jit/lsrabuild.cpp

Properly check for the last use of a field of a multi-reg local in Li…

d94f2b8

…nearScan::BuildStoreLocDef() in src/coreclr/jit/lsrabuild.cpp

echesakov force-pushed the StoreLoc-MultiReg-PreferSrcReg branch from 79d3bb6 to d94f2b8 Compare February 11, 2022 19:07

echesakov closed this Feb 14, 2022

echesakov reopened this Feb 14, 2022

dotnet deleted a comment from azure-pipelines bot Feb 14, 2022

echesakov changed the title ~~For MultiRegStoreLoc prefer allocating a local def to the same register as src~~ Couple optimization to MultiRegStoreLoc Feb 15, 2022

echesakov marked this pull request as ready for review February 15, 2022 01:31

dotnet deleted a comment from azure-pipelines bot Feb 15, 2022

echesakov requested a review from kunalspathak February 15, 2022 01:38

kunalspathak approved these changes Feb 15, 2022

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echesakov mentioned this pull request Feb 15, 2022

codegenarmarch.cpp:3201 Assertion failed '(gcInfo.gcRegGCrefSetCur & killMask) == 0' #65395

Closed

echesakov merged commit 19fc306 into dotnet:main Feb 15, 2022

echesakov deleted the StoreLoc-MultiReg-PreferSrcReg branch February 15, 2022 23:33

BruceForstall mentioned this pull request Feb 25, 2022

Test failure System.IO.Compression.ZLibStreamUnitTests.ReadWrite_Success #65476

Closed

BruceForstall mentioned this pull request Feb 26, 2022

Fix GC hole with multi-reg local var stores #65916

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JulieLeeMSFT mentioned this pull request Mar 3, 2022

What's new in .NET 7 Preview 2 [WIP] dotnet/core#7107

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Couple optimization to MultiRegStoreLoc #64857

Couple optimization to MultiRegStoreLoc #64857

echesakov commented Feb 5, 2022 •

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EgorBo commented Feb 17, 2022

Couple optimization to MultiRegStoreLoc #64857

Couple optimization to MultiRegStoreLoc #64857

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