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Removed unreachable instructions. Moved all remaining VEX instruction…
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… from SSE tables

	into proper VEX tables.

	Fixes #213 #199 #193 #195 #196
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John Detter committed Nov 22, 2016
1 parent ff68cf0 commit 2d7be7a
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Showing 2 changed files with 80 additions and 20 deletions.
98 changes: 79 additions & 19 deletions common/src/arch-x86.C
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Original file line number Diff line number Diff line change
Expand Up @@ -309,6 +309,10 @@ enum { /** AUTOGENERATED */
SSEB29_66, SSEB29_F3,
SSEB2A_66, SSEB2A_F3,
SSEB2B_66,
SSEB2C_66,
SSEB2D_66,
SSEB2E_66,
SSEB2F_66,
SSEB30_66, SSEB30_F3,
SSEB31_66, SSEB31_F3,
SSEB32_66, SSEB32_F3,
Expand Down Expand Up @@ -440,9 +444,11 @@ SSET00 = 0, SSET01, SSET02, SSET03, SSET04, SSET05, SSET06,
enum { /** AUTOGENERATED */
SSET00_66 = 0,
SSET01_66,
SSET02_66,
SSET03_66,
SSET04_66,
SSET05_66,
SSET06_66,
SSET08_66,
SSET09_66,
SSET0A_66,
Expand Down Expand Up @@ -478,6 +484,7 @@ enum { /** AUTOGENERATED */
SSET3F_66,
SSET42_66,
SSET44_66,
SSET46_66,
SSET4A_66,
SSET4B_66,
SSET4C_66,
Expand Down Expand Up @@ -3953,13 +3960,13 @@ static ia32_entry sseMap[][4] = {
{ /* SSE2C */
{ e_cvttps2pi, t_done, 0, true, { Pq, Wps, Zz }, 0, s1W2R },
{ e_cvttss2si, t_sse_mult, SSE2C_F3, true, { Gv, Wss, Zz }, 0, s1W2R },
{ e_cvttpd2pi, t_done, 0, true, { Qdq, Wpd, Zz }, 0, s1W2R },
{ e_cvttpd2pi, t_done, 0, true, { Pdq, Wpd, Zz }, 0, s1W2R },
{ e_cvttsd2si, t_sse_mult, SSE2C_F2, true, { Gv, Wsd, Zz }, 0, s1W2R },
},
{ /* SSE2D */
{ e_cvtps2pi, t_done, 0, true, { Qq, Wps, Zz }, 0, s1W2R },
{ e_cvtps2pi, t_done, 0, true, { Pq, Wps, Zz }, 0, s1W2R },
{ e_cvtss2si, t_sse_mult, SSE2D_F3, true, { Gv, Wss, Zz }, 0, s1W2R },
{ e_cvtpd2pi, t_done, 0, true, { Qdq, Wpd, Zz }, 0, s1W2R },
{ e_cvtpd2pi, t_done, 0, true, { Pdq, Wpd, Zz }, 0, s1W2R },
{ e_cvtsd2si, t_sse_mult, SSE2D_F2, true, { Gv, Wsd, Zz }, 0, s1W2R },
},
{ /* SSE2E */
Expand Down Expand Up @@ -4751,13 +4758,13 @@ static ia32_entry sseMapBis[][5] = {
}, { /* SSEB0C */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpermilps, t_sse_bis_mult, SSEB0C_66, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB0C_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB0D */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpermilpd, t_sse_bis_mult, SSEB0D_66, true, { Vpd, Hpd, Wpd }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB0D_66, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB0E */
Expand Down Expand Up @@ -4811,7 +4818,7 @@ static ia32_entry sseMapBis[][5] = {
}, { /* SSEB16 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpermps, t_sse_bis_mult, SSEB16_66, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB16_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB17 */
Expand Down Expand Up @@ -4943,25 +4950,25 @@ static ia32_entry sseMapBis[][5] = {
}, { /* SSEB2C */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vmaskmovps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB2C_66, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB2D */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vmaskmovpd, t_done, 0, true, { Vpd, Hpd, Wpd }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB2D_66, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB2E */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vmaskmovps, t_done, 0, true, { Wps, Hps, Vps }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB2E_66, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB2F */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vmaskmovpd, t_done, 0, true, { Wpd, Hpd, Vpd }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB2F_66, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB30 */
Expand Down Expand Up @@ -5003,7 +5010,7 @@ static ia32_entry sseMapBis[][5] = {
}, { /* SSEB36 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpermd, t_sse_bis_mult, SSEB36_66, true, { Vdq, Hdq, Wdq }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB36_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB37 */
Expand Down Expand Up @@ -5099,7 +5106,7 @@ static ia32_entry sseMapBis[][5] = {
}, { /* SSEB46 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpsravd, t_sse_bis_mult, SSEB46_66, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_No_Entry, t_sse_bis_mult, SSEB46_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB47 */
Expand Down Expand Up @@ -5636,7 +5643,7 @@ static ia32_entry sseMapTer[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET02 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpblendd, t_done, 0, true, { Vpd, Hpd, Upd }, 0, s1W2R3R4R },
{ e_No_Entry, t_sse_ter_mult, SSET02_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET03 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand All @@ -5652,7 +5659,7 @@ static ia32_entry sseMapTer[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET06 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vperm2f128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_No_Entry, t_sse_ter_mult, SSET06_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET08 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -5704,7 +5711,7 @@ static ia32_entry sseMapTer[][3] =
{ e_extractps, t_done, 0, true, { Ed, Vdq, Ib }, 0, s1W2R3R },
}, { /* SSET18 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vinsertf128, t_sse_ter_mult, SSET18_66, true, { Vdq, Hps, Wps }, 0, s1W2R3R4R },
{ e_No_Entry, t_sse_ter_mult, SSET18_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
}, { /* SSET19 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -5776,7 +5783,7 @@ static ia32_entry sseMapTer[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET38 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vinserti128, t_sse_ter_mult, SSET38_66, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_No_Entry, t_sse_ter_mult, SSET38_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
}, { /* SSET39 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -5816,7 +5823,7 @@ static ia32_entry sseMapTer[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
}, { /* SSET46 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vperm2i128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_No_Entry, t_sse_ter_mult, SSET46_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET4A */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -6912,6 +6919,22 @@ ia32_entry sseMapBisMult[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpackusdw, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_vpackusdw, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
}, { /* SSEB2C_66 */
{ e_vmaskmovps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_vmaskmovps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
{ e_vmaskmovps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
}, { /* SSEB2D_66 */
{ e_vmaskmovpd, t_done, 0, true, { Vpd, Hpd, Wpd }, 0, s1W2R3R },
{ e_vmaskmovpd, t_done, 0, true, { Vpd, Hpd, Wpd }, 0, s1W2R3R },
{ e_vmaskmovpd, t_done, 0, true, { Vpd, Hpd, Wpd }, 0, s1W2R3R },
}, { /* SSEB2E_66 */
{ e_vmaskmovps, t_done, 0, true, { Wps, Hps, Vps }, 0, s1W2R3R },
{ e_vmaskmovps, t_done, 0, true, { Wps, Hps, Vps }, 0, s1W2R3R },
{ e_vmaskmovps, t_done, 0, true, { Wps, Hps, Vps }, 0, s1W2R3R },
}, { /* SSEB2F_66 */
{ e_vmaskmovpd, t_done, 0, true, { Wpd, Hpd, Vpd }, 0, s1W2R3R },
{ e_vmaskmovpd, t_done, 0, true, { Wpd, Hpd, Vpd }, 0, s1W2R3R },
{ e_vmaskmovpd, t_done, 0, true, { Wpd, Hpd, Vpd }, 0, s1W2R3R },
}, { /* SSEB30_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpmovzxbw, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R },
Expand Down Expand Up @@ -7389,6 +7412,10 @@ ia32_entry sseMapTerMult[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpermpd, t_done, 0, true, { Wpd, Vpd, Ib }, 0, s1W2R3R },
{ e_vpermpd, t_done, 0, true, { Vpd, Hpd, Ib }, 0, s1W2R3R },
}, { /* SSET02_66 */
{ e_vpblendd, t_done, 0, true, { Vpd, Hpd, Upd }, 0, s1W2R3R4R },
{ e_vpblendd, t_done, 0, true, { Vpd, Hpd, Upd }, 0, s1W2R3R4R },
{ e_vpblendd, t_done, 0, true, { Vpd, Hpd, Upd }, 0, s1W2R3R4R },
}, { /* SSET03_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand All @@ -7401,6 +7428,10 @@ ia32_entry sseMapTerMult[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpermilpd, t_done, 0, true, { Wpd, Vpd, Ib }, 0, s1W2R3R },
{ e_vpermilpd, t_done, 0, true, { Wpd, Vpd, Ib }, 0, s1W2R3R },
}, { /* SSET06_66 */
{ e_vperm2f128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_vperm2f128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_vperm2f128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
}, { /* SSET08_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -7541,6 +7572,10 @@ ia32_entry sseMapTerMult[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vpclmullqlqdq, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
}, { /* SSET46_66 */
{ e_vperm2i128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_vperm2i128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_vperm2i128, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
}, { /* SSET4A_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vblendvps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
Expand Down Expand Up @@ -8581,6 +8616,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
{
ia32_prefixes& pref = instruct.prf;
unsigned int table, nxtab, idx;
bool vextab = false; /* Did we end in a table that supports VEX? */
int sseidx = 0;
ia32_entry* gotit = NULL;
int condbits = 0;
Expand Down Expand Up @@ -8654,7 +8690,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
gotit = &oneByteMap[idx];
nxtab = gotit->otable;
}

if(capa & IA32_DECODE_CONDITION)
{
assert(instruct.cond != NULL);
Expand All @@ -8665,6 +8701,8 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
while(nxtab != t_done)
{
table = nxtab;
vextab = false;

switch(table)
{
case t_twoB:
Expand Down Expand Up @@ -8758,6 +8796,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
fprintf(stderr, "NEXT TAB == VEXW? %s\n", nxtab == t_vexw ? "YES" : "NO");
#endif

vextab = true;
break;
case t_sse_bis:
/* Decode the sse prefix for this type */
Expand Down Expand Up @@ -8799,6 +8838,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
#ifdef VEX_DEBUG
fprintf(stderr, "SSEB MULT idx: %d sseMul: %d\n", idx, pref.vex_sse_mult);
#endif
vextab = true;
break;
case t_sse_ter:
/* Decode the sse prefix for this type */
Expand Down Expand Up @@ -8838,6 +8878,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
#ifdef VEX_DEBUG
fprintf(stderr, "SSET MULT idx: %d sseMul: %d\n", idx, pref.vex_sse_mult);
#endif
vextab = true;
break;

case t_grp:
Expand Down Expand Up @@ -8867,6 +8908,8 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
gotit = &groupMap2[idx-Grp12][mod==3][reg];
nxtab = gotit->otable;
}

vextab = true;
break;
}
case t_grpsse:
Expand All @@ -8888,8 +8931,10 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
// sseidx >>= 1;
idx = gotit->tabidx;
if(pref.vex_present)
{
gotit = &ssegrpMap_VEX[idx][sseidx];
else
vextab = true;
} else
gotit = &ssegrpMap[idx][sseidx];

nxtab = gotit->otable;
Expand Down Expand Up @@ -8929,6 +8974,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
gotit = &vex2Map[idx][pref.vex_ll];
/* Set the next table - this is almost always t_done */
nxtab = gotit->otable;
vextab = true;
break;
case t_vexw:
/* This MUST have a vex prefix and must NOT be VEX2 */
Expand Down Expand Up @@ -8977,6 +9023,8 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
instruct.entry = gotit;
return -1;
}

vextab = true;
break;
case t_sse_vex_mult:
/* Get the SSE entry */
Expand Down Expand Up @@ -9005,6 +9053,7 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
} else gotit = &sseVexMult[idx][0];

nxtab = gotit->otable;
vextab = true;
break;
case t_ill:
#ifdef VEX_DEBUG
Expand All @@ -9027,6 +9076,17 @@ int ia32_decode_opcode(unsigned int capa, const unsigned char* addr,
}
}

/* If we have a vex prefex, we need to be in a VEX table */
if(pref.vex_present && !vextab)
{
#ifdef VEX_DEBUG
printf("ERROR: This instruction doesn't support VEX prefixes.\n");
#endif
instruct.legacy_type = ILLEGAL;
instruct.entry = gotit;
return -1;
}

/* We should have a valid decoding or we should have returned by now */
assert(gotit != NULL);
instruct.legacy_type = gotit->legacyType;
Expand Down
2 changes: 1 addition & 1 deletion instructionAPI/src/InstructionDecoder-x86.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1009,7 +1009,7 @@ namespace Dyninst
// Selects a general purpose register from VEX.vvvv (VEX3 or EVEX)
if(!pref.vex_present)
{
assert(!"Non VEX3 or EVEX instruction with am_B addressing mode!");
// assert(!"Non VEX3 or EVEX instruction with am_B addressing mode!");
return false;
}

Expand Down

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