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updates to top level caravel #59
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- add patch file for power routing def
- gl - mag - def - add caravel power routing def
… caravel_re-routing
This reverts commit b70c27c.
isolated ground marker layer on the xres_buf layout. Corrected the power supply pin names on the gate level verilog netlist of simple_por in caravel.v. Updated the copyright block text. Corrected DRC errors in the top level routing.
jeffdi
approved these changes
Apr 8, 2022
M0stafaRady
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that referenced
this pull request
Sep 30, 2022
* REVERT ME: temporarily match simple_por pin in verilog with lef * - update configs - add patch file for power routing def * - update the following caravel toplevel views - gl - mag - def - add caravel power routing def * Apply automatic changes to Manifest and README.rst * update gl mag and def for caravel * Revert "REVERT ME: temporarily match simple_por pin in verilog with lef" This reverts commit b70c27c. * update caravel gds * Apply automatic changes to Manifest and README.rst * Added text and logo cells back into the caravel top level. Put an isolated ground marker layer on the xres_buf layout. Corrected the power supply pin names on the gate level verilog netlist of simple_por in caravel.v. Updated the copyright block text. Corrected DRC errors in the top level routing. Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
RTimothyEdwards
added
PnR
Gate level verilog and/or layout changed
flow
Makefile or in-repository flow script changed
labels
Oct 4, 2022
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This PR only updates:
mag
,def
and the verilog gate-level netlistxres_buf
andcopyright_block
.TODO:
simple_por
lef view.