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DMA HAL - clean PR #317
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DMA HAL - clean PR #317
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* Added enums with valid configurations for the DMA
…ess. Also removed re-building of hardware on every run.
…g for the DMA interrupt.
…tion of the intr handler is provided.
…identally modified in previous commit-
…disabled (waiting for functionality from fic).
…example_virtual_flash
…than the integrated one), but changing from one to the other requires an Init()
…idate function called inside the targett validation.
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davideschiavone
requested changes
Jun 23, 2023
int32_t dma_get_done(const dma_t *dma); | ||
typedef enum | ||
{ | ||
DMA_TRANS_MODE_SINGLE = 0, /*!< Only one transaction will be performed.*/ |
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pls referst to the dma_regs.h values rathen than hardcoding 0 and 1
davideschiavone
requested changes
Jun 23, 2023
@@ -92,6 +95,46 @@ | |||
] | |||
} | |||
] | |||
}, |
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{ name: "MODE",
desc: '''Set the operational mode of the DMA''',
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "0", name: "MODE",
desc: "DMA operation mode",
enum: [
{ value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"},
{ value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"},
]
}
]
},
JuanSapriza
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Jul 10, 2023
Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch>
benoitdenkinger
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Aug 21, 2023
* Updated README file to refer to x-heep repo documentation. * Corrected a typo * Made the link specific to prequisite section * Modified vendor hjson * Update esl_epfl_x_heep to esl-epfl/x-heep@495ad7a Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 495ad7ac19c2bfd6a0cc8c68deafccdfb2f7da3b * update docs (esl-epfl/x-heep#209) (David Mallasén Quintana) * Automatisation of CMake back-end (esl-epfl/x-heep#207) (jmiranda) * Add initial guide on extending X-HEEP with CORE-V-XIF (esl- epfl/x-heep#205) (David Mallasén Quintana) * update app (davide schiavone) * update debug.md (Davide Schiavone) * add FreeRTOS support and CMake compatible sw compilation (esl- epfl/x-heep#191) (jmiranda) * add support for cv32e40x (esl-epfl/x-heep#197) (David Mallasén Quintana) * fix common cell (davide schiavone) * [wip] add support for SkyWater130 and OpenRoad (esl-epfl/x-heep#181) (Davide Schiavone) * add Linux-hosted fpga emulation platform (femu) (esl- epfl/x-heep#189) (Saverio Nasturzio) * fix stepi on cve2 (Schiavone Pasquale Davide) * automatic structs generation (esl-epfl/x-heep#196) (Stefano Albini) * automate peripheral integration (esl-epfl/x-heep#195) (fimtrey) * new gpio from pulp (esl-epfl/x-heep#186) (Davide Schiavone) * clock-gating of peripheral subsystem and memory banks (esl- epfl/x-heep#187) (Saverio Nasturzio) * Auto create virtualenv for FuseSoC + other python scripts (esl- epfl/x-heep#188) (Manuel Eggimann) * fix apps and linker script (esl-epfl/x-heep#176) (Simone Machetti) * add spi2 in peripheral domain (esl-epfl/x-heep#180) (Davide Schiavone) * Fixed error in block diagram. (esl-epfl/x-heep#178) (Simone Machetti) * Update README.md (Davide Schiavone) * Added block diagrams. (esl-epfl/x-heep#177) (Simone Machetti) * Update README.md (Davide Schiavone) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Modified internal sw structure * Modified folder structure to be compatible with the new compilation flow * renamed the x-heep vendor files * Update esl_epfl_x_heep to esl-epfl/x-heep@c87d7ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision c87d7ea9888a4353177b76b790019cf1c0c2c481 * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Added vendor file (was not untracked before). * Major changes to make the cgra code compile * Made the necessary changes for verilator-sim to work * Updated a name in func_test main.c * It is possible to simulate a test from uppermost source folder, with cgra, via make run PROJECT=cgra_dbl_search * Compiles both CGRA apps, now includes .c files in the project folder * Made changes in Compilation flow to include files from linked folders. * Reduced the CMakeLists to make it more scalable. * Cleaned up the CMakelists a bit * Added / around the folder criteria to add files to list to prevent files with keywords in the name from being added. * Updated the CMakelist to match changes done in x-heep branch (not yet merged, but to prevent missing this by mistake) * Updated the vendor file to include a specific SHA * Update esl_epfl_x_heep to esl-epfl/x-heep@95256ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 95256ea6f01b665222be18c05ead2da1303729b8 * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * updated the README to point to the vendorized documentation. * Updated vendor file to add fpga board files * Update esl_epfl_x_heep to esl-epfl/x-heep@158a70c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 158a70c92b16a7ab207fe25eae6e131e461d631d * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * In this configuration it is possible to make vivado-fpga. CGRA working on FPGA * Cleaned the files modified for the synthesis for fpga * Restored the CGRA files to they original values and added external cgra_fpga files. Synthezised and tested on FPGA * Removed some changes done inside the cgra * Fixed some names that were modified in previous commits. * Removed visibility signals where they didnt belong so it could be built for simulation * Removed unnecessary signals * Added some commands to quickly load into the fpga * Updated CMakeLists.txt file from x-heep to allow seemless building of apps in the x-heep repo * Added the License file * Renamed vendor files for consistency with lint checks * Updated the vendor sha * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Reformated files * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * formatted with verible * Added verible command to mcu-gen, which was lost * Modified the README to direct to the vendorized X-HEEP prerequisistes * Corrected a typo * Removed unnecessary content from core * Updated the mcu-gen of the topmost Makefile to call the one from X-HEEP and only afterwards call the mc_gen.py with the testbench. * Changed the EXT_XBAR_NMASTER param for EXT_DOMAINS_RND to comply with the changes of #247. Now mcu-gen EXTERNAL_DOMAINS=4 is needed. Also had to add dummy (unused) logic variables or otherwise a variable would be flagged as unused. * Improved the names of the dummy variables * Moved the xilinx_cgra_x_heep_wrapper int othe fpga_cgra folder. * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@a22056c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision a22056c135460b3eb5193caf2fce7e431230393f * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Added the CGRA PLIC interrupt * CGRA dbl search working * cgra functional test working * Do not continue with mcu-gen if there was an error * Updated names to comply with changes in X-HEEP * Changed the use of EXTERNAL_DOMAINS back to EXT_XBAR_NMASTER in cgra_x_heep_top * Can be implemented, but chraseh on CGRA memory access * Crashes on read * :wip: fix external domain * almost fix vendor * add .venv symbolink link * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@435c869 Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Removed virtual environment that was being pushed. Updated pins from new peripherals in X-HEEp * Successfully simulated i nverilator * cgra_func_test working on verilator * Both apps working on FPGA * Updated lint CI to make venv * Added the venv activation * Added non-picocom option to run on the FPGA * Added comment on how to run on fpga in the README file * Remove unused top parameter for external devices. * Verible formating and x-heep tb linked file removed. Automatically generated tb utils file removed. * Append target dependency to app and clean-app to create a link in the sw folder for simpler acces to compiled files. * Added default project name to build app. * README udpated. * README cleaned. * Undo wrong change on vendor file. * Makefile update for questasim run target. * Updated Makefile and README for questasim. * reverting change to cmake targets.mak. * Solving problem with Makefile target dependencies not working. * typos corrected in CGRA code. --------- Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> Co-authored-by: Benoît Denkinger <benoit.denkinger@epfl.ch>
JuanSapriza
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Oct 5, 2023
Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 086884bed017d7778d1c6309533fdf0505a220e2 * Improved the comments on the eXtendingHEEP readme (esl- epfl/x-heep#360) (JuanSapriza) * Modified the way of realizing if an app is external or not (JuanSapriza) * add script to simulate all apps (esl-epfl/x-heep#341) (JuanSapriza) * [app] fix APPs on flash_exec (esl-epfl/x-heep#357) (Davide Schiavone) * adding attributes and mux pad parameters in mcu-gen (esl- epfl/x-heep#349) (Davide Schiavone) * change signal names in power manager to reflex polarity (esl- epfl/x-heep#352) (Simone Machetti) * fix power gating core app (esl-epfl/x-heep#355) (Davide Schiavone) * add cv32e40px (esl-epfl/x-heep#353) (Davide Schiavone) * moved fpnew in its own directory (esl-epfl/x-heep#351) (Davide Schiavone) * update cv32e40p divider (esl-epfl/x-heep#350) (Davide Schiavone) * fix external pad gen (esl-epfl/x-heep#346) (Davide Schiavone) * fix mcu-gen (esl-epfl/x-heep#345) (Davide Schiavone) * update GPIO driver (esl-epfl/x-heep#246) (Hossein Taji) * fix interleaved bus (esl-epfl/x-heep#340) (Daniel Vázquez) * fix esl-epfl/x-heep#338 (esl-epfl/x-heep#339) (Davide Schiavone) * Initialized variables to 0 inside functions. Removed printf comments (esl-epfl/x-heep#334) (JuanSapriza) * made the dma_is_ready() function non-optimizable at all. (esl- epfl/x-heep#333) (JuanSapriza) * fix SPI apps (esl-epfl/x-heep#327) (Davide Schiavone) * Include x-heep.h to all apps that need it (esl-epfl/x-heep#329) (JuanSapriza) * Added soc_ctrl-reg_top warning to waiver (esl-epfl/x-heep#326) (JuanSapriza) * fix several applications (esl-epfl/x-heep#325) (Davide Schiavone) * Tries to use cmake3. If that is not available, go ahead with cmake (esl-epfl/x-heep#323) (JuanSapriza) * Improve the timing of cv32e40x by removing the debug triggers (esl- epfl/x-heep#324) (David Mallasén Quintana) * refactoring of examples (esl-epfl/x-heep#322) (JuanSapriza) * expose internal master ports to external devices (esl- epfl/x-heep#268) (Michele Caon) * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch>
JuanSapriza
added a commit
to esl-epfl/HEEPsilon
that referenced
this pull request
Oct 23, 2023
* Updated README file to refer to x-heep repo documentation. * Corrected a typo * Made the link specific to prequisite section * Modified vendor hjson * Update esl_epfl_x_heep to esl-epfl/x-heep@495ad7a Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 495ad7ac19c2bfd6a0cc8c68deafccdfb2f7da3b * update docs (esl-epfl/x-heep#209) (David Mallasén Quintana) * Automatisation of CMake back-end (esl-epfl/x-heep#207) (jmiranda) * Add initial guide on extending X-HEEP with CORE-V-XIF (esl- epfl/x-heep#205) (David Mallasén Quintana) * update app (davide schiavone) * update debug.md (Davide Schiavone) * add FreeRTOS support and CMake compatible sw compilation (esl- epfl/x-heep#191) (jmiranda) * add support for cv32e40x (esl-epfl/x-heep#197) (David Mallasén Quintana) * fix common cell (davide schiavone) * [wip] add support for SkyWater130 and OpenRoad (esl-epfl/x-heep#181) (Davide Schiavone) * add Linux-hosted fpga emulation platform (femu) (esl- epfl/x-heep#189) (Saverio Nasturzio) * fix stepi on cve2 (Schiavone Pasquale Davide) * automatic structs generation (esl-epfl/x-heep#196) (Stefano Albini) * automate peripheral integration (esl-epfl/x-heep#195) (fimtrey) * new gpio from pulp (esl-epfl/x-heep#186) (Davide Schiavone) * clock-gating of peripheral subsystem and memory banks (esl- epfl/x-heep#187) (Saverio Nasturzio) * Auto create virtualenv for FuseSoC + other python scripts (esl- epfl/x-heep#188) (Manuel Eggimann) * fix apps and linker script (esl-epfl/x-heep#176) (Simone Machetti) * add spi2 in peripheral domain (esl-epfl/x-heep#180) (Davide Schiavone) * Fixed error in block diagram. (esl-epfl/x-heep#178) (Simone Machetti) * Update README.md (Davide Schiavone) * Added block diagrams. (esl-epfl/x-heep#177) (Simone Machetti) * Update README.md (Davide Schiavone) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Modified internal sw structure * Modified folder structure to be compatible with the new compilation flow * renamed the x-heep vendor files * Update esl_epfl_x_heep to esl-epfl/x-heep@c87d7ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision c87d7ea9888a4353177b76b790019cf1c0c2c481 * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Added vendor file (was not untracked before). * Major changes to make the cgra code compile * Made the necessary changes for verilator-sim to work * Updated a name in func_test main.c * It is possible to simulate a test from uppermost source folder, with cgra, via make run PROJECT=cgra_dbl_search * Compiles both CGRA apps, now includes .c files in the project folder * Made changes in Compilation flow to include files from linked folders. * Reduced the CMakeLists to make it more scalable. * Cleaned up the CMakelists a bit * Added / around the folder criteria to add files to list to prevent files with keywords in the name from being added. * Updated the CMakelist to match changes done in x-heep branch (not yet merged, but to prevent missing this by mistake) * Updated the vendor file to include a specific SHA * Update esl_epfl_x_heep to esl-epfl/x-heep@95256ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 95256ea6f01b665222be18c05ead2da1303729b8 * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * updated the README to point to the vendorized documentation. * Updated vendor file to add fpga board files * Update esl_epfl_x_heep to esl-epfl/x-heep@158a70c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 158a70c92b16a7ab207fe25eae6e131e461d631d * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * In this configuration it is possible to make vivado-fpga. CGRA working on FPGA * Cleaned the files modified for the synthesis for fpga * Restored the CGRA files to they original values and added external cgra_fpga files. Synthezised and tested on FPGA * Removed some changes done inside the cgra * Fixed some names that were modified in previous commits. * Removed visibility signals where they didnt belong so it could be built for simulation * Removed unnecessary signals * Added some commands to quickly load into the fpga * Added the venv to the gitignore * Moved the core and added the kernel applications * Removed rand because was not allwing to build * Can run bitcount. Removed unnecessary printfs * Updated the gsm project structure * Added gsm folder * Restructured how kernels are organized in folders. * Restructure is working, but gets errors * Restructure is working, but gets errors * Stats are reported both in tabbed and latex format * Produces a neat outut with average and variance values * Made 250 iterations. Dies @ 500 * Now values are presented in cycles * Prints the ratio between cgra and software execution * Addded utility scripts * Added a plot to see the active cycles distribution in time * Previous to trying new generator * Multiple kernels are run, but results vary in unomalous ways * added edadk.conf and env.sh * Added scripts for simulation and synthesis. Problemas with including packages * Multiple kernels cannot be run one after the other * Can make questasim-sim suceesfully * Added pin toggle and reduced the number of unneccessary printfs * Gets the cycle count considering the delay of writing register. Accurate ~3 cycles * Now prints std deviation instead of variance * Added a larger access flat cost to match. Timer cycles match reported cycles. * Added the reversebit kernel. Runs, but no in conjuntion with other kernels. It seems they are not re-configuring * Reorganized the process of launching kernels, but the second kernel is not configured * Change the kernel id on each kernel change. Now they cofigure properly. Added the possibility of configuring the vcd trigger by gpio * Moved functions to kernel commons. Fixed sqrt. Fixed some lucky situations concerning interrupts. GSM can break if a printf is put between the kernel launch and the wait for interrupt. * Major refactoring and commenting of the heeptest_gen.py. Generated and added sha2, but results in errors. * GSM is working with new changes in heeptest_gen * Changed the information of the sha2 io.json and the heeptest_gen so that the cgra_output is taken from the correct field * With the modifications in the io.json and heeptest_gen every kernel is running without errors. * From the kernel common header you can choose to print all the cgra results and the comparison with software * Added sha and sqrt, but none of them work properly * Rebuilt the old kernels so that they are all under the same script. Had to fix io.json of gsm that was working because there was a bug and the in vars had depth 1 * bitcount, reversebits, sha2 and gsm without errors * bitcount, reversebits, gsm, sha and sha2 work. Only 4 kernels work toghether, the fifth gets stuck or returns errors. * Modified path to kernel_commons from header template * Intermediate commit * Corrected gsm kernel. Addd a debug option for sqrt, which is not working. Added watchdog for broken kernels. * To test on Questasim * Some modification on the patch modelsim * Made some modifications to the strsearch function and source file to debug * Adapted the way of accessing inputs and outputs from the kernel_commons. GSM works with old confi now. Must re-do all kernels * Sqrt inputs limited to positive numbers * All kernels working independently, but not toghther * imem is now a constant, but still not many kernels can be run at the same time * 6 kernels can be run, but only up to 5 iterations, no prints apart from the summaries. Bitcount is broken * All kernels can be run, up to 5 iterations * Beginning of stringsearch tests * Made some modifications to the instr-encoder so that the strsearch kernel could be re-generated. Now it runs, but gives a wrong answer * C function is working * C function is working * To test signals * Passing patlen -2 allows strsearch to finish properly, but always returns skip2 * With the corrected kernel assembly the str search kernels seems to work * Stringsearch working, but lowercase conversion failing * string search is generally working. Only starnge case in last commit is pending * Tests with fixed patterns * Fixed pattern tests with updated assembly from USI * Updated CMakeLists.txt file from x-heep to allow seemless building of apps in the x-heep repo * Added the License file * Moved the cgra-x_heep_core to the base folder, as it was preventing the make vivado-fpga * Re-generated the bitstream from the assembly from USI * Added fixed arrays for testing * reverted changes to cgra.sv * Added the exit command to the assembly, which was causing the app to crash * Patched scrit and added core to allow questasim-sim-opt * Updated the bitstream to a working one * Added changes in logic of RCs. Still changing last value of result RC * Cleaned the modifications in the cgra.sv file. This works both on Questasim and FPGA. * Brought changes tested on kernel_test_sim to to use in the FPGA * The 7 kernels can be run on the pynq-z2 * Removed wrong comment * Renamed vendor files for consistency with lint checks * Updated the vendor sha * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Reformated files * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * formatted with verible * Added verible command to mcu-gen, which was lost * Modified the README to direct to the vendorized X-HEEP prerequisistes * Corrected a typo * Removed unnecessary content from core * Updated the mcu-gen of the topmost Makefile to call the one from X-HEEP and only afterwards call the mc_gen.py with the testbench. * Changed the EXT_XBAR_NMASTER param for EXT_DOMAINS_RND to comply with the changes of #247. Now mcu-gen EXTERNAL_DOMAINS=4 is needed. Also had to add dummy (unused) logic variables or otherwise a variable would be flagged as unused. * Improved the names of the dummy variables * Moved the xilinx_cgra_x_heep_wrapper int othe fpga_cgra folder. * Fixed the computation of the deviation. Still some differences with post-synthesis simulation * Added the generation of new VCD files by toggling of GPIO * Adapted for FPGA. Running * Re-adapted the value to be substarcted to the time measured * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@a22056c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision a22056c135460b3eb5193caf2fce7e431230393f * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Added the CGRA PLIC interrupt * CGRA dbl search working * cgra functional test working * Do not continue with mcu-gen if there was an error * Updated names to comply with changes in X-HEEP * Changed the use of EXTERNAL_DOMAINS back to EXT_XBAR_NMASTER in cgra_x_heep_top * Can be implemented, but chraseh on CGRA memory access * Crashes on read * :wip: fix external domain * almost fix vendor * add .venv symbolink link * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@435c869 Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Removed virtual environment that was being pushed. Updated pins from new peripherals in X-HEEp * Successfully simulated i nverilator * cgra_func_test working on verilator * Both apps working on FPGA * Updated lint CI to make venv * Added the venv activation * Added non-picocom option to run on the FPGA * Added comment on how to run on fpga in the README file * Updated so to run apps in the FPGA * Kernel test working for 4x4 * Convolution running sucessfully in software * Added a 3x3 convolution - most basic example * Test for convolution * Fixed conflict in tb * Added temporary register to verilator waiver * Updated the links to the tb_top * Removed a vscode folder --------- Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> Co-authored-by: Sapriza Juan <sapriza@eslsrv12.intranet.epfl.ch>
JuanSapriza
added a commit
to esl-epfl/HEEPsilon
that referenced
this pull request
Oct 23, 2023
* Updated README file to refer to x-heep repo documentation. * Corrected a typo * Made the link specific to prequisite section * Modified vendor hjson * Update esl_epfl_x_heep to esl-epfl/x-heep@495ad7a Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 495ad7ac19c2bfd6a0cc8c68deafccdfb2f7da3b * update docs (esl-epfl/x-heep#209) (David Mallasén Quintana) * Automatisation of CMake back-end (esl-epfl/x-heep#207) (jmiranda) * Add initial guide on extending X-HEEP with CORE-V-XIF (esl- epfl/x-heep#205) (David Mallasén Quintana) * update app (davide schiavone) * update debug.md (Davide Schiavone) * add FreeRTOS support and CMake compatible sw compilation (esl- epfl/x-heep#191) (jmiranda) * add support for cv32e40x (esl-epfl/x-heep#197) (David Mallasén Quintana) * fix common cell (davide schiavone) * [wip] add support for SkyWater130 and OpenRoad (esl-epfl/x-heep#181) (Davide Schiavone) * add Linux-hosted fpga emulation platform (femu) (esl- epfl/x-heep#189) (Saverio Nasturzio) * fix stepi on cve2 (Schiavone Pasquale Davide) * automatic structs generation (esl-epfl/x-heep#196) (Stefano Albini) * automate peripheral integration (esl-epfl/x-heep#195) (fimtrey) * new gpio from pulp (esl-epfl/x-heep#186) (Davide Schiavone) * clock-gating of peripheral subsystem and memory banks (esl- epfl/x-heep#187) (Saverio Nasturzio) * Auto create virtualenv for FuseSoC + other python scripts (esl- epfl/x-heep#188) (Manuel Eggimann) * fix apps and linker script (esl-epfl/x-heep#176) (Simone Machetti) * add spi2 in peripheral domain (esl-epfl/x-heep#180) (Davide Schiavone) * Fixed error in block diagram. (esl-epfl/x-heep#178) (Simone Machetti) * Update README.md (Davide Schiavone) * Added block diagrams. (esl-epfl/x-heep#177) (Simone Machetti) * Update README.md (Davide Schiavone) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Modified internal sw structure * Modified folder structure to be compatible with the new compilation flow * renamed the x-heep vendor files * Update esl_epfl_x_heep to esl-epfl/x-heep@c87d7ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision c87d7ea9888a4353177b76b790019cf1c0c2c481 * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Added vendor file (was not untracked before). * Major changes to make the cgra code compile * Made the necessary changes for verilator-sim to work * Updated a name in func_test main.c * It is possible to simulate a test from uppermost source folder, with cgra, via make run PROJECT=cgra_dbl_search * Compiles both CGRA apps, now includes .c files in the project folder * Made changes in Compilation flow to include files from linked folders. * Reduced the CMakeLists to make it more scalable. * Cleaned up the CMakelists a bit * Added / around the folder criteria to add files to list to prevent files with keywords in the name from being added. * Updated the CMakelist to match changes done in x-heep branch (not yet merged, but to prevent missing this by mistake) * Updated the vendor file to include a specific SHA * Update esl_epfl_x_heep to esl-epfl/x-heep@95256ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 95256ea6f01b665222be18c05ead2da1303729b8 * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * updated the README to point to the vendorized documentation. * Updated vendor file to add fpga board files * Update esl_epfl_x_heep to esl-epfl/x-heep@158a70c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 158a70c92b16a7ab207fe25eae6e131e461d631d * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * In this configuration it is possible to make vivado-fpga. CGRA working on FPGA * Cleaned the files modified for the synthesis for fpga * Restored the CGRA files to they original values and added external cgra_fpga files. Synthezised and tested on FPGA * Removed some changes done inside the cgra * Fixed some names that were modified in previous commits. * Removed visibility signals where they didnt belong so it could be built for simulation * Removed unnecessary signals * Added some commands to quickly load into the fpga * Added the venv to the gitignore * Moved the core and added the kernel applications * Removed rand because was not allwing to build * Can run bitcount. Removed unnecessary printfs * Updated the gsm project structure * Added gsm folder * Restructured how kernels are organized in folders. * Restructure is working, but gets errors * Restructure is working, but gets errors * Stats are reported both in tabbed and latex format * Produces a neat outut with average and variance values * Made 250 iterations. Dies @ 500 * Now values are presented in cycles * Prints the ratio between cgra and software execution * Addded utility scripts * Added a plot to see the active cycles distribution in time * Previous to trying new generator * Multiple kernels are run, but results vary in unomalous ways * added edadk.conf and env.sh * Added scripts for simulation and synthesis. Problemas with including packages * Multiple kernels cannot be run one after the other * Can make questasim-sim suceesfully * Added pin toggle and reduced the number of unneccessary printfs * Gets the cycle count considering the delay of writing register. Accurate ~3 cycles * Now prints std deviation instead of variance * Added a larger access flat cost to match. Timer cycles match reported cycles. * Added the reversebit kernel. Runs, but no in conjuntion with other kernels. It seems they are not re-configuring * Reorganized the process of launching kernels, but the second kernel is not configured * Change the kernel id on each kernel change. Now they cofigure properly. Added the possibility of configuring the vcd trigger by gpio * Moved functions to kernel commons. Fixed sqrt. Fixed some lucky situations concerning interrupts. GSM can break if a printf is put between the kernel launch and the wait for interrupt. * Major refactoring and commenting of the heeptest_gen.py. Generated and added sha2, but results in errors. * GSM is working with new changes in heeptest_gen * Changed the information of the sha2 io.json and the heeptest_gen so that the cgra_output is taken from the correct field * With the modifications in the io.json and heeptest_gen every kernel is running without errors. * From the kernel common header you can choose to print all the cgra results and the comparison with software * Added sha and sqrt, but none of them work properly * Rebuilt the old kernels so that they are all under the same script. Had to fix io.json of gsm that was working because there was a bug and the in vars had depth 1 * bitcount, reversebits, sha2 and gsm without errors * bitcount, reversebits, gsm, sha and sha2 work. Only 4 kernels work toghether, the fifth gets stuck or returns errors. * Modified path to kernel_commons from header template * Intermediate commit * Corrected gsm kernel. Addd a debug option for sqrt, which is not working. Added watchdog for broken kernels. * To test on Questasim * Some modification on the patch modelsim * Made some modifications to the strsearch function and source file to debug * Adapted the way of accessing inputs and outputs from the kernel_commons. GSM works with old confi now. Must re-do all kernels * Sqrt inputs limited to positive numbers * All kernels working independently, but not toghther * imem is now a constant, but still not many kernels can be run at the same time * 6 kernels can be run, but only up to 5 iterations, no prints apart from the summaries. Bitcount is broken * All kernels can be run, up to 5 iterations * Beginning of stringsearch tests * Made some modifications to the instr-encoder so that the strsearch kernel could be re-generated. Now it runs, but gives a wrong answer * C function is working * C function is working * To test signals * Passing patlen -2 allows strsearch to finish properly, but always returns skip2 * With the corrected kernel assembly the str search kernels seems to work * Stringsearch working, but lowercase conversion failing * string search is generally working. Only starnge case in last commit is pending * Tests with fixed patterns * Fixed pattern tests with updated assembly from USI * Updated CMakeLists.txt file from x-heep to allow seemless building of apps in the x-heep repo * Added the License file * Moved the cgra-x_heep_core to the base folder, as it was preventing the make vivado-fpga * Re-generated the bitstream from the assembly from USI * Added fixed arrays for testing * reverted changes to cgra.sv * Added the exit command to the assembly, which was causing the app to crash * Patched scrit and added core to allow questasim-sim-opt * Updated the bitstream to a working one * Added changes in logic of RCs. Still changing last value of result RC * Cleaned the modifications in the cgra.sv file. This works both on Questasim and FPGA. * Brought changes tested on kernel_test_sim to to use in the FPGA * The 7 kernels can be run on the pynq-z2 * Removed wrong comment * Renamed vendor files for consistency with lint checks * Updated the vendor sha * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Reformated files * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * formatted with verible * Added verible command to mcu-gen, which was lost * Modified the README to direct to the vendorized X-HEEP prerequisistes * Corrected a typo * Removed unnecessary content from core * Updated the mcu-gen of the topmost Makefile to call the one from X-HEEP and only afterwards call the mc_gen.py with the testbench. * Changed the EXT_XBAR_NMASTER param for EXT_DOMAINS_RND to comply with the changes of #247. Now mcu-gen EXTERNAL_DOMAINS=4 is needed. Also had to add dummy (unused) logic variables or otherwise a variable would be flagged as unused. * Improved the names of the dummy variables * Moved the xilinx_cgra_x_heep_wrapper int othe fpga_cgra folder. * Fixed the computation of the deviation. Still some differences with post-synthesis simulation * Added the generation of new VCD files by toggling of GPIO * Adapted for FPGA. Running * Re-adapted the value to be substarcted to the time measured * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@a22056c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision a22056c135460b3eb5193caf2fce7e431230393f * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Added the CGRA PLIC interrupt * CGRA dbl search working * cgra functional test working * Do not continue with mcu-gen if there was an error * Updated names to comply with changes in X-HEEP * Changed the use of EXTERNAL_DOMAINS back to EXT_XBAR_NMASTER in cgra_x_heep_top * Can be implemented, but chraseh on CGRA memory access * Crashes on read * :wip: fix external domain * almost fix vendor * add .venv symbolink link * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@435c869 Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> * Removed virtual environment that was being pushed. Updated pins from new peripherals in X-HEEp * Successfully simulated i nverilator * cgra_func_test working on verilator * Both apps working on FPGA * Updated lint CI to make venv * Added the venv activation * Added non-picocom option to run on the FPGA * Added comment on how to run on fpga in the README file * Updated so to run apps in the FPGA * Kernel test working for 4x4 * Convolution running sucessfully in software * Added a 3x3 convolution - most basic example * Test for convolution * Fixed conflict in tb * Added temporary register to verilator waiver * Updated the links to the tb_top * Removed a vscode folder * Removed sudo from run commands on makefile and left repo running reversebits --------- Signed-off-by: Juan Sapriza <juan.sapriza@epfl.ch> Co-authored-by: Sapriza Juan <sapriza@eslsrv12.intranet.epfl.ch>
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We have made this PR so that Github shows a more accurate representation of the actual differences between this branch and main.
Please refer to conversation in this PR.
I leave the documentation below.
DMA
The Direct Memory Access (DMA) peripheral allows data transfers with reduced CPU interaction.
It can perform transactions of data between peripherals and memory, or memory-to-memory (as a
memcpy
would).The CPU is required to configure the transaction, but once launched it is free to go to sleep, process the incoming data or do anything else.
The DMA HAL
The DMA Hardware Abstraction Layer (HAL) facilitates the configuration of transactions from the users application. Furthermore, it adds an additional layer of safety checks to reduce the risk of faulty memory accesses, data override or infinite loops.
Previous Definitions
The implementation of this software layer introduced some concepts that need to be understood in order to make proper use of the DMA's functionalities .
Transaction
A transaction is an operation to be performed by the DMA. It implies copying bytes from a source pointer into a destination pointer. The transaction configuration can be loaded into the DMA registers once it has been cross-checked and it only starts when the size of the transaction is written in its corresponding register. The transaction is finished once the DMA has sent all its bytes (which not necessarily means they have been received by the final destination).
Transactions cannot be stopped once they were launched.
While a transaction is running, new transactions can be validated, but not launched or loaded into the DMA.
Transactions can be re-launched automatically in
circular mode
.Once the transaction has finished, a status bit is changed (that can be monitored through polling) and a fast interrupt is triggered.
Source and destination
Sources and destinations are the two pointers that will exchange data. Bytes will be copied from the source and into the destination address.
Data type
The DMA allows transactions in chunks of 1, 2 or 4 Bytes (
Byte
,Half-Word
andWord
respectively). The size in bytes of the chosen data type is called data unit (usually abbreviated asdu
).For example, 16 bytes can be 16 data units if the data type is
Byte
, but 8 data units if the data type isHalf Word
.Increment
In the case that source and/or destination data are not to be consecutively read/written, a certain increment can be defined.
For instance, if you have an array of 4-bytes-words, but only want to copy the first 2 bytes of each word, you could define the transaction with a data type of half word, an increment of 2 data units in the source, and 1 data unit in the destination. This way, after each read operation the DMA will increment the read pointer in 4 bytes (2 data units), but the write pointer by only 2 bytes.
Alignment
When doing transactions with bytes, the DMA can read/write from any pointer. However, if the data type is larger, words should be aligned so the DMA can perform a read/write operation and affect only the chosen bytes. If a word or half-word's pointer is not a multiple of 4 or 2 (respectively), the pointer is misaligned. In some cases the DMA HAL can overcome this problem reducing the data type (which will reflect on an efficiency loss).
Environment
An environment is a region of memory that can optionally be defined by the user to let the HAL know that it is allowed to read/write on that region. It is useful to make sure the DMA will not affect reserved memory regions.
Right now, read and write permissions are not supported by environments, meaning that if it is defined, the DMA will be able to read AND write on it.
Triggers and Slots
If the source or destination pointer is a peripheral, there are lines connecting the peripheral and the DMA that can be used to control the data flow (they behave as triggers). These lines are connected to slots on the DMA and they allow/stop the DMA from reading/writing data.
Target
A target is either a region of memory or a peripheral to which the DMA will be able to read/write. When targets are pointing to memory, they can be assigned an environment to make sure that they will comply with memory restrictions.
Targets include a pointer (a point in the memory, or the Rx/Tx buffer in case of peripherals), a size to be copied (if its going to be used as a source), a data type and an increment.
Configuration flags
During the creation or configuration of environments, targets or transactions, there could be inconsistencies or threatening situations (like writing outside the boundaries of a defined region). To provide the user with information about this potentially harmful situations, configuration flags are set while creating each of these entities. They can be unmasked and checked.
In some cases, when the threat is too risky, a crucial error might be raised and the operation of the configuration is halted.
If senseless configurations are input to functions, assertions may halt the whole program. This is reserved for extreme situations that mean the program was not properly coded (e.g. a slot value is provided and is not among the available ones).
Transaction modes
There are three different transaction modes:
Single Mode: The default mode, where the DMA will perform the copy from the source target to the destination, and trigger an interrupt once done.
Circular mode: To take full advantage of the speed and transparency of the DMA, a circular mode was implemented. When selected, the DMA will relaunch the exactly same transaction upon finishing. This cycle only stops if by the end of a transaction the transaction mode was changed to single. The CPU receives a fast interrupt on every transaction finished.
Address Mode: Instead of using the destination pointer and increment to decide where to copy information, an address list must be provided, containing addresses for each data unit being copied. It is only carried out in single mode.
Windows
In order to process information as it arrives, the application can define a window size (smaller than the transaction size. Every time the DMA has finished sending that given amount of information will trigger an interrupt through the PLIC.
Checks and Validations
The DMA HAL's interface functions perform two types of checks:
Checks and validations are performed during the transactions creation, loading and launching.
A transaction is validated if it went through the creation-checks without raising critical errors.
End events
The DMA considers a certain amount of bytes to have been transferred once it has sent them. It does not wait for a confirmation from the recipient. When a transaction/window is finished the DMA performs a series of event. These may include:
The DMA HAL can follow up on these changes or let the application be in charge. For this purpose, three different types of end events are defined:
wfi()
state until the transaction done interrupt is triggered.Operation
This section will explain the operation of the DMA through the DMA HAL.
There is a DMA instance inside X-HEEP, but others can be connected outside through the bus (see the
example_external_peripheral
application insw/aplications/example_external_peripheral/main.c
). As long as the DMA instance is the same and the registers are memory mapped with the same structure, the DMA HAL can be used.The DMA HAL adds an extra computational overhead to transactions in order to check the consistency of the transaction configurations. By-passing this layer (and the steps here described) is disadvised. For the efficiency-hungry applications, doing at least one pass with the whole validation process is recommended. The HAL allows to load and launch transactions with minimum overhead afterwards.
The following explanation makes use of Figure 1.
Figure 1: Example operation of the DMA and its HAL
The use of the DMA starts with the application creating a set of targets (a) . In the figure, the source target is a peripheral connected to an SPI and to the DMA. The address of the reception FIFO (Rx FIFO) of this SPI is
0x70
(b) . The destination target is a region of memory of address0x16
(c). It is located inside an environment that spans from0x12
to0x35
. Any number of environments and targets can be created, and not used.Additionally, in the application the transaction is created. The operation mode and window size are selected.
The application calls the validation function of the HAL. If the configurations do not raise a critical flag, it then calls the loading function. By doing so, the desired values are written into their corresponding registers (d). The only register that is not immediately written is the transaction size, as it is the one responsible for launching the transaction when changed from zero to a non-zero value. It is only written once the application calls the launching function (e).
Note that there could be some changes between the configuration input in the application and the values written in the registers. For example, a window size of 2 refers to 2 data units (i.e. 2 half-words, as such is the data type of the source in Figure 1); however, when writing on the register, this is translated to bytes, so 4 is written instead.
Once launched, the transaction will execute completely (it cannot be stopped). Upon finishing, it will check the operation mode and transaction size registers. If any of both is non-zero, it will relaunch. Note that the selecting circular mode during the configuration loading does not launch the transaction (despite what step (f) might suggest, which is only illustrative).
Once the transaction is launched, the DMA will take care of copying as many data units as were requested from the source target (g), and pasting them into the destination target (h). The data width of the transaction is determined by the data type of the source target (i). However, this might be changed (for a smaller width) in case of misalignment. It is possible to reject changes by the DMA HAL and raise an error in case of misalignments instead.
The selected slot will query the state of a trigger from the peripheral (j). In case the peripheral's FIFO is empty/full (for reception/transmission respectively), the transaction is paused until the trigger enables it again.
The source and destination increments will determine the amount of steps the pointer should jump after every read and write, respectively. For peripherals it should always be zero (as it should always take the first element of the FIFO).
The DMA will consider a data unit was transferred once it is sent (k). It does not wait for an acknowledge by the destination target.
The interrupts register controls whether the events triggered by the DMA upon finishing a window or a whole transaction should be propagated as interrupts (l).
Every time window size data units have been transferred the window count is incremented and a PLIC interrupt is triggered (if enabled) (m).
Every time a transaction is finished a FIC interrupt is triggered and the restart condition is evaluated (f).
If the window size is a multiple of the transaction size, upon finishing the transaction there will be first an interrupt for the whole transaction (through the FIC), and then an interrupt for the window (through the PLIC, which is slower).
The DMA HAL has weak implementations to handle each interrupt. It is up to the application to do something useful with this. the HAL will only forward the interrupt (n).
The same result from this example could have been achieved by setting the transaction mode to address. It requires an array of destination addresses (p) that must be provided as the destination target pointer. Instead of copying information to that pointer, the DMA will read from there and copy the information into the addresses stored in each word (o).
This use case is very impractical as it doubles the memory usage. It is intended to be used along In-Memory-Computing architectures and algorithms.
Usage
This section will explain a basic usage of the DMA as a
memcpy
, and a slightly more complex situation involving a peripheral connected via an SPI.Basic application
This example will provide a simplified code for copying data from one region of memory to another. For a real implementation please refer to the
dma_example
application insw/applications/dma_example/main.c
.The objective of this app would be to copy the content of an array into another.
Start the application by calling
This will reset the DMA registers. The
NULL
parameter tells the HAL that the devices internal DMA is to be used.The most basic implementation requires the creation of two targets and a transaction relating them both.
A target will include the information of the source or destination pointer and the characteristics of the expected transaction.
Theoretically, there is no required difference between a source and destination target. They will only be differentiated once the transaction is created. Eventually, they could be interchanged from one transaction to the next. In this example they will be given explicit names and will take different arguments for the sake of clarity.
Here,
ptr = copy_buffer
is auint32_t
pointer from where the information will be extracted.inc_du = 1
is telling the DMA that for each word copied, the pointer should be incremented by 1 unit, therefore words will be copied consecutively without gaps.This configuration is implicitly initializing the rest of the target configurations as zero (as of C99). This means that:
The destination target can also dispense of a size, as the source size will be used.
Finally, a transaction is created to relate both targets:
This will also imply some configurations set to zero:
The transaction can now be created (some extra configurations are computed from the targets), loaded into the DMA and launched.
When creating the transaction, the two last parameters are allowing the DMA to perform integrity checks and try some fixes (at the expense of efficiency) if misalignments are found.
As there will be no interrupts set, the application has to check by itself the status of the transaction.
Complete Application
The objective of this example is to show various special cases, precautions and considerations that can be taken. For a real example refer to the
spi_flash_write
application insw/applications/spi_flash_write/main.c
.This example will copy every other byte from a buffer in RAM to a FLASH connected via an SPI to the DMA. Then, it will copy information from an SPI peripheral continuously into a small buffer.
This explanation assumes you have read the previous example.
Start the application by calling
The first source target will be pointing to a
uint16_t
buffer in memory. Data will be copied in chunks of 1 byte. For every half-word (16 bits), the only the second half (second 8 bits) will be copied.To start copying information from the second byte of
copy_buffer
, the source pointer is set to the address ofcopy_buffer
plus one byte.In order to copy one byte and skip another, the data type is set to byte, and the increment is set to two data units (i.e. two bytes). As for every half-word of the buffer a data unit will be copied, the transaction size is the same as the size of the
copy_buffer
.The second target will point to the address of the SPI FLASH transmission FIFO. On this example, this value was already computed and stored in a constant
ADDRESS_SPI_FLASH_TX_FIFO
.Because structure initializers need to be constants, the pointer value (which is a non-constant variable) needs to be initialized outside the designated initializer.
There is no need to assign a value of transaction size or data type. By default, the DMA will use the source's values. The data type could eventually be modified by the HAL if there is a misalignment and
DMA_ENABLE_REALIGN
is set when creating the transaction.The increment needs to be set to zero as the pointer should always be set to the FIFO address.
Because the SPI FLASH transmission FIFO has a line connected to slot number 4 (codified as a
1
in the fourth bit of thetrig
element) to let the DMA know if the FIFO is full, a trigger is set in that position by passing.trig = DMA_TRIG_SLOT_SPI_FLASH_TX
.The transaction is formed by selecting the source and destination targets
To enable interrupts, the end event is set to
DMA_TRANS_END_INTR
.To create the transaction allowing the DMA to perform necessary realignments and integrity checks such arguments are passed to the creation function along with a pointer to the transaction.
The result variable
res
contains configuration flags that can be used to check that no errors or warnings were raised. These are codified as bits in the 16-bitres
variable.If only one flag was raised, the value of
res
will be equal to it. Otherwise, they can be checked by selecting individual bits, with inequalities, or comparing the result to a bitwise-or of flags.The transaction can then be loaded into the DMA registers by calling the load function
and launched
Because the DMA will raise an interrupt as soon as it has sent all of its information, it is recommended to wait for the SPI interrupt.
If something is to be done as soon as the DMA finishes (like preparing a new transaction) it can be triggered by the interrupt attention routine:
This function is a strong implementation defined in the application of the weak one in
dma.c
.During this transaction
B
in the chart below).D
from the chart.L
) is sent to the SPI.For the second part of this example, the targets will be modified and their role switched.
The source of the data will be a peripheral connected to the SPI, which will be continuously sending information in half-word format, in streams of 4096 bytes (2048 half-words). Every 1024 half-words there should be a
MILESTONE-CHARACTER
, if there is not, the data flow should be stopped.The source pointer is set to the reception FIFO of the SPI, and the appropriate slot is chosen.
The increment is kept in zero.
The destination pointer will be given by a function.
To guarantee that the result of this function will not cause the DMA to write in undesired regions of memory, an environment can be created.
It requires two pointers to the first and last byte where the DMA will be authorized to make any action.
The environment can be assigned to the target.
Size and data type is up to the source, and the rest of the configurations are inherited from the last transaction.
The transaction is conformed as:
Meaning that the information will start to flow into the target 1 from target 2, and every 1024 half-words transferred the application will get an interrupt to check if the
MILESTONE_SYMBOL
is present. Upon finishing the transaction, it shall start again to refill the buffer as it was set inCIRCULAR_MODE
.The amount of times the buffer was filled will be updated on every transaction done interrupt.
The search for the
MILESTONE_SYMBOL
can be done inside the window done interrupt handling.Once the
dma_stop_circular()
function is called, the DMA will still finish the transaction it is currently executing (which could be a whole transaction if the faulty window was the last one). It is important to save valuable information that might be overridden by the ongoing transaction (like the faulty window number).Testing
This section will describe the available example application in X-HEEP using the DMA, and will outline the testing that needs to be performed in order to validate its proper operation.
Available Applications
There are 6 applications using the DMA:
dma_example
: Tests memory-to-memory transfer, the blocking of transactions while another one is in progress, and window interrupts.example_external_peripheral
: Tests the use of the DMA HAL one a DMA instance external to X-HEEP. Only available for simulation.example_virtual_flash
: Tests the transfer to/from an external flash through the DMA.spi_flash_write
: Tests the transfer to/from the flash. Tests circular mode. Not available on FPGA if linker isflash-exec
. Should be used withmcu gen BUS=NtoM CPU=cv32e40p
to test circular mode.spi_host_dma_exampe
: Test the transfer of data through the SPI host. Not available on Verilator.spi_host_dma_power_gate_example
: Test the transfer of data through the SPI host. Not available on Verilator.White Testing
The white testing of the DMA HAL should be focused on
Pathological scenarios should be prioritized.
Tests should be performed checking flags and doing the suggested validate-load-launch sequence described in prior examples. Failures in the execution as a result of not properly managing the process should not be considered a bug. Checks should always be enabled. Checks without enabling the realignment are suggested, but should not be the norm.
Note that not all elements of a target/transaction need to be filled every time. If filled they might be not used or overridden.
Examples
A transaction where:
should raise a critical error and not be allowed to launch.
A transaction where:
should raise a misalignment flag, perform a realignment (reduce the transaction data type to byte) and perform the transaction.
Tips
To easily detect anomalies I suggest
uint8_t
and filling them with a certain pattern (e.g. a range from 0 to N).uint16_t *misaligned = (uint16_t*)((uint8_t*)buffer + 1);
._du
means the number should be input in data units, while_b
means bytes.Here is a spreadsheet that we can use to analyze all the pathological cases and what is the expected return of the HAL.
It is incomplete, but its a draft that we could use.