SBML missing logic arc

[ugurdogrusoz]

(thanks @adrienrougny) Logic arcs are completely missed in SBML notation. These are needed to connect Species to Logical operators (see the bottom middle part here; edges from D & E to the logical operators are of type logic arc). PD has a counterpart for logical operators. When we implement these, we should also add the rules for creating edges of this type (Species to Logical Operators).

[ugurdogrusoz]

This is from @SelbiEreshova:
Yes, indeed I did not implement a 'Logical operator arc'. Rather, I added rules so we can use existing edges (consumption, catalysis for 'and' and 'or' operator, inhibition for 'not' operator) to construct what we see in Boolean logic gate section.
Here is an 'and' operator I constructed on Newt 4:

We are still talking to find out the motivation for this but we'll properly need to disallow the usage of some arc types on logic gates when we properly implement logic arcs.

[umut-er]

This seems to be a similar issue to #735.

From what I understand, we want the logic arc to connect any node to a logical operator. After that, and, or gates should be able make a single connection to a process node with an edge of type consumption or catalysis. The not gate can use the inhibition edge in addition to those. Is this accurate? Is this the behavior we want? What about trigger edges (see picture above)? What about unknown edges (unknown catalysis, unknown inhibition etc...)? What about reduced edges?

[ugurdogrusoz]

See my email and list the rules as you understand here so I can verify.

[umut-er]

Here is my understanding.

I take that modulating arcs are the second arc division in our current sbml palette. The reduced modulating arcs are the third division.

and / or gates can take as many logic arcs as desired as input but can only have 1 modulating (or reduced modulating) arc as output. not gate can only take in one input logic arc but otherwise is the same as the other ones.

Is that accurate @ugurdogrusoz?

PS. Maybe we should name the second division modulating arcs and the third reduced modulating arcs.

[ugurdogrusoz]

Yes that sounds correct. I am not sure about naming that's why the separation without naming.

[umut-er]

This issue is almost done on my part. However, there is one issue:

(The arcs are in the order they are in the palette) As you can see, for the majority of arcs, there is a port connection issue. This is probably because these arcs usually don't originate from a process (see the compartment on the right). However, for a minority of arcs, we get the intended behavior, which means that there is a (relatively easy?) fix out there. I think Noor should take a look at this because he was working on #735, which, from the outside, looks very similar. If these issues are unrelated, I can work on a fix.

[umut-er]

Assigning to @ugurdogrusoz for now. You can check the rules for connecting logical operators and the logic arc. The port issue I outlined still remains however.

[ugurdogrusoz]

@umut-er Looks good in general except:

• 1. Logical operator --Inhibition--> Omitted process gives an error in the Console and does not work

[ugurdogrusoz]

@NoorMuhammad1 Let's make sure

• 2. All Logical Arcs that connect a Species (Phenotype excluded) to a Logical Operator use a proper port (input port of the Logical Operator). Currently Unknown Logical Operator is the only problem one here.

• 3. All modulation arcs listed below connect Logical Operators to their target Process nodes (Association and Dissociation excluded) from a port (output port of the Logical Operator). Currently, Unknown Catalysis and Unknown Inhibition are the only problem ones. Also (see comment below for @umut-er about constructing an Inhibition; you should test the situation with this modulation arc after that problem is fixed).

[umut-er]

All modulation arcs listed below connect Logical Operators to their target Process nodes (Association and Dissociation excluded) from a port (output port of the Logical Operator). Currently, Unknown Catalysis and Unknown Inhibition are the only problem ones. Also (see comment below for @umut-er about constructing an Inhibition; you should test the situation with this modulation arc after that problem is fixed).

Shouldn't the reduced modulation arcs (i.e. the third group of edges, see my message) also connect to the output port of the logical operator? Also, isn't there a problem with the trigger edge in the row you indicated?

Logical operator --Inhibition--> Omitted process gives an error in the Console and does not work

Should be fixed. It was caused by a typo.

[NoorMuhammad1]

I fixed both the issues. The problem was that the code looks for different types of pre-defined set of arcs to know if they should be connected at the ports or not. I just added the arcs that were missing from the list and added a new option to check for logic arc.

[ugurdogrusoz]

All modulation arcs listed below connect Logical Operators to their target Process nodes (Association and Dissociation excluded) from a port (output port of the Logical Operator). Currently, Unknown Catalysis and Unknown Inhibition are the only problem ones. Also (see comment below for @umut-er about constructing an Inhibition; you should test the situation with this modulation arc after that problem is fixed).

Shouldn't the reduced modulation arcs (i.e. the third group of edges, see my message) also connect to the output port of the logical operator? Also, isn't there a problem with the trigger edge in the row you indicated?

I think not since they are directly between Species, do not go through process nodes.

[ugurdogrusoz]

3. Modulation arcs (including Unknown Catalysis and Unknown Inhibition) now connect Logical Operators from their output ports but they should not use input ports to connect to processes. This can be seen in the related table.

[NoorMuhammad1]

The issue for 3. Modulation arcs connecting to ports of processes while joining logical operators with the process is solved. I added the option to check if the arc was a modulation arc and the target node was a process node. And then if it is true then the arc is not connected to the target node ports.

[ugurdogrusoz]

@hasanbalci @umut-er Can you guys test this as well? Looked good to me.

[hasanbalci]

I didn't see any problem either.

[umut-er]

I think it is good to go.