Chipathon2024 saltychip

[tsengs0]

Current progress of the team SaltyChip

1. transmission gate: the first version of the layout generation is completed but some modifications/improvements are needed.
2. MIM capacitor array: the layout is still under development.

[chetanyagoyal]

Can you please convert this to a draft PR is work is yet to be completed?

[tsengs0]

This work is not completed yet, so we converted this pull request to a draft.

[alibillalhammoud]

Hey guys, thanks for the contribution please check out

OpenFASOC/openfasoc/generators/glayout/glayout/flow/primitives/mimcap.py

Line 90 in e7f4611

def mimcap_array(pdk: MappedPDK, rows: int, columns: int, size: tuple[float,float] = (5.0,5.0), rmult: Optional[int]=1) -> Component:

[tsengs0]

We have added our working directory of the transmission gate, so we would like make a pull request for the PR draft of our work.
The description about the PCell is in the README.md under the directory transmission_gate.

Layout generated by using glayout

Three GDS of PCell layout is generated as depicted below.

• Transmission gate with W/L=2um / 0.15um for all PMOS and NMOS
  

• Transmission gate with W/L=12um / 0.15um for all PMOS and NMOS
  

• Transmission gate with W/L=24um / 0.15um for all PMOS and NMOS

Progress

• Magic DRC: clean without error
• LVS: pin mismatched has not been resolved yet. We faced a difficulty in directly generating a correct netlist using the glayout and also none of us is familiar with the Netgen tool, so the netlist generation and LVS error fixing are still ongoing.

Failed LVS report (corresponded to the design of W/L=12 um / 0.15 um)

Circuit 1 cell sky130_fd_pr__pfet_01v8 and Circuit 2 cell sky130_fd_pr__pfet_01v8 are black boxes.
Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__pfet_01v8         |Circuit 2: sky130_fd_pr__pfet_01v8         
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
4                                          |4                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.

Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_01v8         |Circuit 2: sky130_fd_pr__nfet_01v8         
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
4                                          |4                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.

Class tg_cell_471429cf (0):  Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: tg_cell_471429cf                |Circuit 2: tg_cell_471429cf                
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8 (6->3)             |sky130_fd_pr__pfet_01v8 (4->1) **Mismatch* 
sky130_fd_pr__nfet_01v8 (6->3)             |sky130_fd_pr__nfet_01v8 (4->1) **Mismatch* 
Number of devices: 6 **Mismatch**          |Number of devices: 2 **Mismatch**          
Number of nets: 10 **Mismatch**            |Number of nets: 6 **Mismatch**             
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: tg_cell_471429cf                |Circuit 2: tg_cell_471429cf                

---------------------------------------------------------------------------------------
Net: w_n715_603#                           |Net: VDD                                   
  sky130_fd_pr__pfet_01v8/4 = 3            |  sky130_fd_pr__pfet_01v8/4 = 1            
                                           |                                           
Net: a_n877_n684#                          |Net: VSS                                   
  sky130_fd_pr__nfet_01v8/4 = 3            |  sky130_fd_pr__nfet_01v8/4 = 1            
---------------------------------------------------------------------------------------
Netlists do not match.

Subcircuit pins:
Circuit 1: tg_cell_471429cf                |Circuit 2: tg_cell_471429cf                
-------------------------------------------|-------------------------------------------
Cell pin lists are equivalent.
Device classes tg_cell_471429cf and tg_cell_471429cf are equivalent.

Final result: Netlists do not match.

[alibillalhammoud]

thanks for the PR. LGTM

[alibillalhammoud]

thanks for the PR. LGTM