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Chipathon2024 saltychip#347

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tsengs0 wants to merge 21 commits intoidea-fasoc:mainidea-fasoc/OpenFASOC:mainfrom tsengs0:chipathon2024_saltychiptsengs0/OpenFASOC:chipathon2024_saltychipCopy head branch name to clipboard

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Commits

Commits on Nov 3, 2024

• Add the transmission gate (still onging) folder from the SaltyChi team in Chipathon 2024

  tsengs0

  committed
  1a3770b

• Add the README and __init__.py files for the transmission gate block

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  tsengs0

  committed
  0377bae

• Add mimcap array layout

  tsengs0

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  5d7dc55

• Update the progress in the README

  tsengs0

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  23738f6

Commits on Nov 8, 2024

• Modify the layout of the transmission by rotating every MOSFET 90 degree

  tsengs0

  committed
  de306c8

Commits on Nov 10, 2024

• Add dummy cells to the PMOS-NMOS pair for the TG against the asymmetical layout (form of parallel-gate transistors)

  tsengs0

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  b1d1ae0

• Complete routing of the TG w/ an inverter for controlling the gates of the TG's PMOS and NMOS

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  tsengs0

  committed
  ecabeed

• Add the first draft of layout report and GDS w/o I/O port yet

  tsengs0

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  929bf0b

Commits on Nov 13, 2024

• Add the external I/O ports for the transmission gate

  tsengs0

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  e5e9a2c

Commits on Nov 14, 2024

• Create a Colab notebook generating and displaying the transmission gate's GDSII image, according to the main layout work in "transmission_gate.py" and "eval.py".

  tsengs0

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  4830dce

• Add functions to automatically insert the external I/O ports on the target Pcell

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  477ff15

Commits on Nov 15, 2024

• Add the ToDo list for the PR draft submission

  tsengs0

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  e034352

Commits on Nov 17, 2024

• Change the route layer inside the transmission gate

  tsengs0

  committed
  94561b6

• Add the external pins for the LVS process

  tsengs0

  committed
  6d8e8be

• Team: Salty Chip, Chipathon2024

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  tsengs0

  committed
  c75a0a5

Commits on Nov 18, 2024

• Team: Salty Chip, Chipathon2024

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  cc695ac

Commits on Nov 20, 2024

• Team: Salty Chip, Chipathon2024

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  tsengs0

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  84b94b3

Commits on Nov 21, 2024

• Team: Salty Chip, Chipathon2024

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  tsengs0

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  351cbdf

Commits on Nov 23, 2024

• Final modification of the intergititized layout of the transmission gate PCell

  tsengs0

  committed
  8bd30da

• Modify the netlist gen for the transmission gate

  tsengs0

  committed
  6d79564

Commits on Nov 24, 2024

• Contributor: Team SaltyChip, Chipathon 2024

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  0fcd05a