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Various Fixes
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@calebbiggers
calebbiggers committed Dec 2, 2024
1 parent 69f412c commit b1bee44
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Showing 38 changed files with 2,040 additions and 876 deletions.
32 changes: 16 additions & 16 deletions ADL/metrics/alderlake_metrics_goldencove_core.json
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14 changes: 7 additions & 7 deletions ADL/metrics/perf/alderlake_metrics_goldencove_core_perf.json
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Expand Up @@ -89,7 +89,7 @@
},
{
"BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
"MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + ma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )",
"MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )",
"MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots",
"MetricName": "tma_bottleneck_other_bottlenecks",
"MetricThreshold": "tma_bottleneck_other_bottlenecks > 20",
Expand Down Expand Up @@ -1099,7 +1099,7 @@
"MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0",
"MetricGroup": "Cor;SMT;Metric",
"MetricName": "tma_info_botlnk_l0_core_bound_likely",
"MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5"
"MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5"
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
Expand Down Expand Up @@ -1419,23 +1419,23 @@
"MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )",
"MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_misses",
"MetricThreshold": "tma_info_botlnk_dsb_misses > 10",
"MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10",
"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp."
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck",
"MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )",
"MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_bandwidth",
"MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10",
"MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10",
"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp."
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck",
"MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )",
"MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL",
"MetricName": "tma_info_botlnk_l2_ic_misses",
"MetricThreshold": "tma_info_botlnk_ic_misses > 5",
"MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5",
"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck."
},
{
Expand Down Expand Up @@ -1618,7 +1618,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
"MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
Expand Down Expand Up @@ -1667,7 +1667,7 @@
"MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )",
"MetricGroup": "Prefetches;Metric",
"MetricName": "tma_info_memory_prefetches_useless_hwpf",
"MetricThreshold": "tma_info_memory_useless_hwpf > 0.15"
"MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15"
},
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
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34 changes: 17 additions & 17 deletions ARL/metrics/arrowlake_metrics_lioncove_core.json
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Expand Up @@ -2,7 +2,7 @@
"Header": {
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Metrics for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture0",
"DatePublished": "11/15/2024",
"DatePublished": "12/02/2024",
"Version": "1.0",
"Legend": "",
"TmaVersion": "5.01",
Expand Down Expand Up @@ -8234,11 +8234,11 @@
},
{
"Alias": "b",
"Value": "tma_info_thread_ipc"
"Value": "metric_TMA_Info_Thread_IPC"
}
],
"Formula": "a < 0.7 & b / 8 > 0.35",
"BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & tma_info_thread_ipc / 8 > 0.35",
"BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 8 > 0.35",
"ThresholdIssues": "$issueFB"
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -8706,11 +8706,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Botlnk_DSB_Misses"
"Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses"
}
],
"Formula": "a > 10",
"BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10",
"BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10",
"ThresholdIssues": "$issueFB"
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -8790,11 +8790,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth"
"Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth"
}
],
"Formula": "a > 10",
"BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10",
"BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10",
"ThresholdIssues": "$issueFB"
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -8870,11 +8870,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Botlnk_IC_Misses"
"Value": "metric_TMA_Info_Botlnk_L2_IC_Misses"
}
],
"Formula": "a > 5",
"BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5",
"BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5",
"ThresholdIssues": "$issueFL"
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -9966,11 +9966,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Memory_Page_Walks_Utilization"
"Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization"
}
],
"Formula": "a > 0.5",
"BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5",
"BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5",
"ThresholdIssues": ""
},
"ResolutionLevels": "CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -10096,11 +10096,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret"
"Value": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret"
}
],
"Formula": "a > 0.05",
"BaseFormula": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret > 0.05",
"BaseFormula": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret > 0.05",
"ThresholdIssues": ""
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -10136,11 +10136,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret"
"Value": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret"
}
],
"Formula": "a > 0.05",
"BaseFormula": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret > 0.05",
"BaseFormula": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret > 0.05",
"ThresholdIssues": ""
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -10176,11 +10176,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Memory_Useless_HWPF"
"Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF"
}
],
"Formula": "a > 0.15",
"BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15",
"BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15",
"ThresholdIssues": ""
},
"ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",
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14 changes: 7 additions & 7 deletions ARL/metrics/perf/arrowlake_metrics_lioncove_core_perf.json
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Expand Up @@ -1379,23 +1379,23 @@
"MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )",
"MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_misses",
"MetricThreshold": "tma_info_botlnk_dsb_misses > 10",
"MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10",
"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp."
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck",
"MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )",
"MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_bandwidth",
"MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10",
"MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10",
"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp."
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck",
"MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )",
"MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL",
"MetricName": "tma_info_botlnk_l2_ic_misses",
"MetricThreshold": "tma_info_botlnk_ic_misses > 5",
"MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5",
"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck."
},
{
Expand Down Expand Up @@ -1591,7 +1591,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_thread_clks )",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
"MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
Expand All @@ -1616,21 +1616,21 @@
"MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_LOADS * cpu_core@MEM_INST_RETIRED.STLB_MISS_LOADS@R ) / tma_info_thread_clks",
"MetricGroup": "Mem;MemoryTLB;Clocks_Retired",
"MetricName": "tma_info_memory_tlb_load_stlb_miss_ret",
"MetricThreshold": "tma_info_memory_load_stlb_miss_ret > 0.05"
"MetricThreshold": "tma_info_memory_tlb_load_stlb_miss_ret > 0.05"
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores",
"MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_STORES * cpu_core@MEM_INST_RETIRED.STLB_MISS_STORES@R ) / tma_info_thread_clks",
"MetricGroup": "Mem;MemoryTLB;Clocks_Retired",
"MetricName": "tma_info_memory_tlb_store_stlb_miss_ret",
"MetricThreshold": "tma_info_memory_store_stlb_miss_ret > 0.05"
"MetricThreshold": "tma_info_memory_tlb_store_stlb_miss_ret > 0.05"
},
{
"BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses",
"MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )",
"MetricGroup": "Prefetches;Metric",
"MetricName": "tma_info_memory_prefetches_useless_hwpf",
"MetricThreshold": "tma_info_memory_useless_hwpf > 0.15"
"MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15"
},
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
Expand Down
10 changes: 5 additions & 5 deletions BDW/metrics/broadwell_metrics.json
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Expand Up @@ -2,7 +2,7 @@
"Header": {
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Metrics for 5th Generation Intel(R) Core(TM) Processor0",
"DatePublished": "11/15/2024",
"DatePublished": "12/02/2024",
"Version": "1.0",
"Legend": "",
"TmaVersion": "5.01",
Expand Down Expand Up @@ -5090,11 +5090,11 @@
},
{
"Alias": "b",
"Value": "tma_info_thread_ipc"
"Value": "metric_TMA_Info_Thread_IPC"
}
],
"Formula": "a < 0.7 & b / 4 > 0.35",
"BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35",
"BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35",
"ThresholdIssues": "$issueFB"
},
"ResolutionLevels": "CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -5700,11 +5700,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Memory_Page_Walks_Utilization"
"Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization"
}
],
"Formula": "a > 0.5",
"BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5",
"BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5",
"ThresholdIssues": ""
},
"ResolutionLevels": "CORE, SOCKET, SYSTEM",
Expand Down
2 changes: 1 addition & 1 deletion BDW/metrics/perf/broadwell_metrics_perf.json
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Original file line number Diff line number Diff line change
Expand Up @@ -927,7 +927,7 @@
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=0x1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / tma_info_core_core_clks",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
"MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
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10 changes: 5 additions & 5 deletions BDX/metrics/broadwellx_metrics.json
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Expand Up @@ -2,7 +2,7 @@
"Header": {
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor E5 v4 Family Based on the Broadwell Microarchitecture0",
"DatePublished": "11/15/2024",
"DatePublished": "12/02/2024",
"Version": "1.0",
"Legend": "",
"TmaVersion": "5.01",
Expand Down Expand Up @@ -6152,11 +6152,11 @@
},
{
"Alias": "b",
"Value": "tma_info_thread_ipc"
"Value": "metric_TMA_Info_Thread_IPC"
}
],
"Formula": "a < 0.7 & b / 4 > 0.35",
"BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35",
"BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35",
"ThresholdIssues": "$issueFB"
},
"ResolutionLevels": "CORE, SOCKET, SYSTEM",
Expand Down Expand Up @@ -6762,11 +6762,11 @@
"ThresholdMetrics": [
{
"Alias": "a",
"Value": "metric_TMA_Info_Memory_Page_Walks_Utilization"
"Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization"
}
],
"Formula": "a > 0.5",
"BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5",
"BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5",
"ThresholdIssues": ""
},
"ResolutionLevels": "CORE, SOCKET, SYSTEM",
Expand Down
2 changes: 1 addition & 1 deletion BDX/metrics/perf/broadwellx_metrics_perf.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1196,7 +1196,7 @@
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * tma_info_core_core_clks )",
"MetricGroup": "Mem;MemoryTLB;Core_Metric",
"MetricName": "tma_info_memory_tlb_page_walks_utilization",
"MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5"
"MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
Expand Down
28 changes: 14 additions & 14 deletions CLX/metrics/cascadelakex_metrics.json
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