[AArch64] Implement TRBMPAM_EL1 system register

[jthackray]

Implement TRBMPAM_EL1 system register, which was noticed to be missing

[llvmbot]

@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-mc

Author: Jonathan Thackray (jthackray)

Changes

Implement TRBMPAM_EL1 system register, which was noticed to be missing

---

Full diff: https://github.com/llvm/llvm-project/pull/102485.diff

3 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+1)
• (modified) llvm/test/MC/AArch64/trbe-sysreg.s (+4)
• (modified) llvm/test/MC/Disassembler/AArch64/trbe.txt (+4)

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 0b5bc97674c768..cd6e6bffda10bc 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1669,6 +1669,7 @@ def : RWSysReg<"TRBPTR_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b001>;
 def : RWSysReg<"TRBBASER_EL1",  0b11, 0b000, 0b1001, 0b1011, 0b010>;
 def : RWSysReg<"TRBSR_EL1",     0b11, 0b000, 0b1001, 0b1011, 0b011>;
 def : RWSysReg<"TRBMAR_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b100>;
+def : RWSysReg<"TRBMPAM_EL1",   0b11, 0b000, 0b1001, 0b1011, 0b101>;
 def : RWSysReg<"TRBTRG_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b110>;
 def : ROSysReg<"TRBIDR_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b111>;
 } // FeatureTRBE
diff --git a/llvm/test/MC/AArch64/trbe-sysreg.s b/llvm/test/MC/AArch64/trbe-sysreg.s
index f9ba076200bbf2..bf02856e5a69d8 100644
--- a/llvm/test/MC/AArch64/trbe-sysreg.s
+++ b/llvm/test/MC/AArch64/trbe-sysreg.s
@@ -8,6 +8,7 @@ mrs x0, TRBPTR_EL1
 mrs x0, TRBBASER_EL1
 mrs x0, TRBSR_EL1
 mrs x0, TRBMAR_EL1
+mrs x0, TRBMPAM_EL1
 mrs x0, TRBTRG_EL1
 mrs x0, TRBIDR_EL1
 
@@ -16,6 +17,7 @@ mrs x0, TRBIDR_EL1
 // CHECK: mrs x0, TRBBASER_EL1  // encoding: [0x40,0x9b,0x38,0xd5]
 // CHECK: mrs x0, TRBSR_EL1     // encoding: [0x60,0x9b,0x38,0xd5]
 // CHECK: mrs x0, TRBMAR_EL1    // encoding: [0x80,0x9b,0x38,0xd5]
+// CHECK: mrs x0, TRBMPAM_EL1   // encoding: [0xa0,0x9b,0x38,0xd5]
 // CHECK: mrs x0, TRBTRG_EL1    // encoding: [0xc0,0x9b,0x38,0xd5]
 // CHECK: mrs x0, TRBIDR_EL1    // encoding: [0xe0,0x9b,0x38,0xd5]
 
@@ -25,6 +27,7 @@ msr TRBPTR_EL1, x0
 msr TRBBASER_EL1, x0
 msr TRBSR_EL1, x0
 msr TRBMAR_EL1, x0
+msr TRBMPAM_EL1, x0
 msr TRBTRG_EL1, x0
 
 // CHECK: msr TRBLIMITR_EL1, x0 // encoding: [0x00,0x9b,0x18,0xd5]
@@ -32,4 +35,5 @@ msr TRBTRG_EL1, x0
 // CHECK: msr TRBBASER_EL1, x0  // encoding: [0x40,0x9b,0x18,0xd5]
 // CHECK: msr TRBSR_EL1, x0     // encoding: [0x60,0x9b,0x18,0xd5]
 // CHECK: msr TRBMAR_EL1, x0    // encoding: [0x80,0x9b,0x18,0xd5]
+// CHECK: msr TRBMPAM_EL1, x0   // encoding: [0xa0,0x9b,0x18,0xd5]
 // CHECK: msr TRBTRG_EL1, x0    // encoding: [0xc0,0x9b,0x18,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/trbe.txt b/llvm/test/MC/Disassembler/AArch64/trbe.txt
index 936b2d3070f7d0..551eae221e408a 100644
--- a/llvm/test/MC/Disassembler/AArch64/trbe.txt
+++ b/llvm/test/MC/Disassembler/AArch64/trbe.txt
@@ -8,6 +8,7 @@
 [0x40,0x9b,0x38,0xd5]
 [0x60,0x9b,0x38,0xd5]
 [0x80,0x9b,0x38,0xd5]
+[0xa0,0x9b,0x38,0xd5]
 [0xc0,0x9b,0x38,0xd5]
 [0xe0,0x9b,0x38,0xd5]
 
@@ -16,6 +17,7 @@
 # CHECK: mrs x0, TRBBASER_EL1
 # CHECK: mrs x0, TRBSR_EL1
 # CHECK: mrs x0, TRBMAR_EL1
+# CHECK: mrs x0, TRBMPAM_EL1
 # CHECK: mrs x0, TRBTRG_EL1
 # CHECK: mrs x0, TRBIDR_EL1
 
@@ -25,6 +27,7 @@
 [0x40,0x9b,0x18,0xd5]
 [0x60,0x9b,0x18,0xd5]
 [0x80,0x9b,0x18,0xd5]
+[0xa0,0x9b,0x18,0xd5]
 [0xc0,0x9b,0x18,0xd5]
 
 # CHECK: msr TRBLIMITR_EL1, x0
@@ -32,4 +35,5 @@
 # CHECK: msr TRBBASER_EL1, x0
 # CHECK: msr TRBSR_EL1, x0
 # CHECK: msr TRBMAR_EL1, x0
+# CHECK: msr TRBMPAM_EL1, x0
 # CHECK: msr TRBTRG_EL1, x0