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[AArch64] Implement TRBMPAM_EL1 system register #102485

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Aug 9, 2024
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[AArch64] Implement TRBMPAM_EL1 system register #102485

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1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1669,6 +1669,7 @@ def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>;
def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>;
def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>;
def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>;
def : RWSysReg<"TRBMPAM_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b101>;
def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>;
def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>;
} // FeatureTRBE
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4 changes: 4 additions & 0 deletions llvm/test/MC/AArch64/trbe-sysreg.s
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Expand Up @@ -8,6 +8,7 @@ mrs x0, TRBPTR_EL1
mrs x0, TRBBASER_EL1
mrs x0, TRBSR_EL1
mrs x0, TRBMAR_EL1
mrs x0, TRBMPAM_EL1
mrs x0, TRBTRG_EL1
mrs x0, TRBIDR_EL1

Expand All @@ -16,6 +17,7 @@ mrs x0, TRBIDR_EL1
// CHECK: mrs x0, TRBBASER_EL1 // encoding: [0x40,0x9b,0x38,0xd5]
// CHECK: mrs x0, TRBSR_EL1 // encoding: [0x60,0x9b,0x38,0xd5]
// CHECK: mrs x0, TRBMAR_EL1 // encoding: [0x80,0x9b,0x38,0xd5]
// CHECK: mrs x0, TRBMPAM_EL1 // encoding: [0xa0,0x9b,0x38,0xd5]
// CHECK: mrs x0, TRBTRG_EL1 // encoding: [0xc0,0x9b,0x38,0xd5]
// CHECK: mrs x0, TRBIDR_EL1 // encoding: [0xe0,0x9b,0x38,0xd5]

Expand All @@ -25,11 +27,13 @@ msr TRBPTR_EL1, x0
msr TRBBASER_EL1, x0
msr TRBSR_EL1, x0
msr TRBMAR_EL1, x0
msr TRBMPAM_EL1, x0
msr TRBTRG_EL1, x0

// CHECK: msr TRBLIMITR_EL1, x0 // encoding: [0x00,0x9b,0x18,0xd5]
// CHECK: msr TRBPTR_EL1, x0 // encoding: [0x20,0x9b,0x18,0xd5]
// CHECK: msr TRBBASER_EL1, x0 // encoding: [0x40,0x9b,0x18,0xd5]
// CHECK: msr TRBSR_EL1, x0 // encoding: [0x60,0x9b,0x18,0xd5]
// CHECK: msr TRBMAR_EL1, x0 // encoding: [0x80,0x9b,0x18,0xd5]
// CHECK: msr TRBMPAM_EL1, x0 // encoding: [0xa0,0x9b,0x18,0xd5]
// CHECK: msr TRBTRG_EL1, x0 // encoding: [0xc0,0x9b,0x18,0xd5]
4 changes: 4 additions & 0 deletions llvm/test/MC/Disassembler/AArch64/trbe.txt
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Expand Up @@ -8,6 +8,7 @@
[0x40,0x9b,0x38,0xd5]
[0x60,0x9b,0x38,0xd5]
[0x80,0x9b,0x38,0xd5]
[0xa0,0x9b,0x38,0xd5]
[0xc0,0x9b,0x38,0xd5]
[0xe0,0x9b,0x38,0xd5]

Expand All @@ -16,6 +17,7 @@
# CHECK: mrs x0, TRBBASER_EL1
# CHECK: mrs x0, TRBSR_EL1
# CHECK: mrs x0, TRBMAR_EL1
# CHECK: mrs x0, TRBMPAM_EL1
# CHECK: mrs x0, TRBTRG_EL1
# CHECK: mrs x0, TRBIDR_EL1

Expand All @@ -25,11 +27,13 @@
[0x40,0x9b,0x18,0xd5]
[0x60,0x9b,0x18,0xd5]
[0x80,0x9b,0x18,0xd5]
[0xa0,0x9b,0x18,0xd5]
[0xc0,0x9b,0x18,0xd5]

# CHECK: msr TRBLIMITR_EL1, x0
# CHECK: msr TRBPTR_EL1, x0
# CHECK: msr TRBBASER_EL1, x0
# CHECK: msr TRBSR_EL1, x0
# CHECK: msr TRBMAR_EL1, x0
# CHECK: msr TRBMPAM_EL1, x0
# CHECK: msr TRBTRG_EL1, x0
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