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[PowerPC] Support conversion between f16 and f128 #97677

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[PowerPC] Support conversion between f16 and f128 #97677

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2684fc1
F16 and f128 conversion.
EsmeYi Jul 4, 2024
0a819fe
For truncation from f128 to f16, always use the lib fucntion (direct …
EsmeYi Jul 25, 2024
46a826c
Updated tests.
EsmeYi Jul 25, 2024
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6 changes: 6 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -210,13 +210,19 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}

setTruncStoreAction(MVT::f128, MVT::f16, Expand);
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nit: could you please add a comment here why we can not use PWR9 instructions to do the conversion.

setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);

if (Subtarget.isISA3_0()) {
setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
setTruncStoreAction(MVT::f64, MVT::f16, Legal);
setTruncStoreAction(MVT::f32, MVT::f16, Legal);
} else {
// No extending loads from f16 or HW conversions back and forth.
setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
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4 changes: 4 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrVSX.td
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Expand Up @@ -3993,6 +3993,8 @@ defm : ScalToVecWPermute<
(SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;

// Load/convert and convert/store patterns for f16.
def : Pat<(f128 (extloadf16 ForceXForm:$src)),
(f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src))))>;
def : Pat<(f64 (extloadf16 ForceXForm:$src)),
(f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
Expand All @@ -4001,6 +4003,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), VSSRC))>;
def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
(STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), ForceXForm:$dst)>;
def : Pat<(f128 (f16_to_fp i32:$A)),
(f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A))))>;
def : Pat<(f64 (f16_to_fp i32:$A)),
(f64 (XSCVHPDP (MTVSRWZ $A)))>;
def : Pat<(f32 (f16_to_fp i32:$A)),
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64 changes: 64 additions & 0 deletions llvm/test/CodeGen/PowerPC/f128-conv.ll
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Expand Up @@ -1450,6 +1450,70 @@ entry:
ret void
}

define half @trunc(fp128 %a) unnamed_addr {
; CHECK-LABEL: trunc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl __trunctfhf2
; CHECK-NEXT: nop
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: trunc:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __trunctfhf2
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: bl __gnu_h2f_ieee
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
entry:
%0 = fptrunc fp128 %a to half
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nit: We'd better avoid the unnamed variable names, like %0. (Suggested by https://llvm.org/docs/TestingGuide.html#writing-new-regression-tests)

ret half %0
}

define fp128 @ext(half %a) unnamed_addr {
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nit: Is the unnamed_addr needed?

; CHECK-LABEL: ext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ext:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
entry:
%0 = fpext half %a to fp128
ret fp128 %0
}

@f128Glob = common global fp128 0xL00000000000000000000000000000000, align 16

; Function Attrs: norecurse nounwind readnone
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17 changes: 17 additions & 0 deletions llvm/test/CodeGen/PowerPC/fp128-libcalls.ll
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Expand Up @@ -30,6 +30,15 @@ define fp128 @divkf3(fp128 %a, fp128 %b) {
ret fp128 %1
}


define fp128 @extendsfkf2_f16(half %a) {
; CHECK-LABEL: extendsfkf2_f16:
; CHECK: __extendsfkf2
entry:
%0 = fpext half %a to fp128
ret fp128 %0
}

define fp128 @extendsfkf2(float %a) {
; CHECK-LABEL: extendsfkf2:
; CHECK: __extendsfkf2
Expand All @@ -44,6 +53,14 @@ define fp128 @extenddfkf2(double %a) {
ret fp128 %1
}

define half @trunctfhf2(fp128 %a) {
; CHECK-LABEL: trunctfhf2:
; CHECK: __trunctfhf2
entry:
%0 = fptrunc fp128 %a to half
ret half %0
}

define float @trunckfsf2(fp128 %a) {
; CHECK-LABEL: trunckfsf2:
; CHECK: __trunckfsf2
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