Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[stm32] Add FDCAN support for H7 series #1206

Merged
merged 5 commits into from
Sep 25, 2024
Merged

[stm32] Add FDCAN support for H7 series #1206

merged 5 commits into from
Sep 25, 2024

Commits on Sep 25, 2024

  1. [stm32] Add FDCAN support for H7 series 

    The H7 series supports a user-configured message RAM layout, rather than
the static layout of past STM32 CAN IPs. The new message RAM is
identical in structure and configurability to the ATSAM FDCAN IP. This
commit merges the STM32 FDCAN and ATSAM FDCAN message RAM
implementations.

For H7 it also introduces lbuild parameters so the user can choose the amount
of space available for each RX queue, each TX queue, and filters. This is
independent for each FDCAN IP instance, although they share the same 10k RAM.
    @WasabiFan
    WasabiFan committed Sep 25, 2024
    Configuration menu
    Copy the full SHA
    ce9c654 View commit details
    Browse the repository at this point in the history

  2. [stm32] Allow using hardware buffers only in FDCAN driver

    @chris-durand @WasabiFan
    chris-durand authored and WasabiFan committed Sep 25, 2024
    Configuration menu
    Copy the full SHA
    a5223aa View commit details
    Browse the repository at this point in the history

  3. [stm32] Default FDCAN to FIFO mode instead of Queue Mode 

    Queue Mode will send CAN frames in priority order according to their
arbitration ID. This is inconsistent with modm's software-managed queue
which is a strict FIFO. To make the behavior of the driver consistent
with an end-to-end FIFO order, we disable Queue Mode by default.

There is a new lbuild option, "tx_hw_queue_mode", which allows the user
to opt back into the old behavior if desired. This is mostly intended
for if they also set "buffer.tx" to zero and optionally increase
"message_ram.tx_fifo_elements".

Note that the fdcan unit test was implicitly assuming FIFO order. This
change also fixes that test for larger HW TX buffer sizes.
    @WasabiFan
    WasabiFan committed Sep 25, 2024
    Configuration menu
    Copy the full SHA
    7a4df09 View commit details
    Browse the repository at this point in the history

  4. [stm32] Remove references to nonexistent 'a0' STM32H7 chip

    @WasabiFan
    WasabiFan committed Sep 25, 2024
    Configuration menu
    Copy the full SHA
    9e7bdf4 View commit details
    Browse the repository at this point in the history

  5. [stm32] Fix initialization of FDCAN message RAM 

    After power-on the FDCAN message RAM is filled with non-zero invalid
data. In some cases the CAN filter region contains well-formed entries
which cause inadvertent reception or rejection of messages.

To prevent this message RAM sections are now zeroed out on the first
initialization of the respective FDCAN instance.
    @chris-durand @WasabiFan
    chris-durand authored and WasabiFan committed Sep 25, 2024
    Configuration menu
    Copy the full SHA
    3614dc0 View commit details
    Browse the repository at this point in the history