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[stm32] Add FDCAN support for H7 series #1206

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merged 5 commits into from
Sep 25, 2024
Merged

[stm32] Add FDCAN support for H7 series #1206

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ce9c654
[stm32] Add FDCAN support for H7 series
WasabiFan Sep 2, 2024
a5223aa
[stm32] Allow using hardware buffers only in FDCAN driver
chris-durand May 15, 2024
7a4df09
[stm32] Default FDCAN to FIFO mode instead of Queue Mode
WasabiFan Sep 16, 2024
9e7bdf4
[stm32] Remove references to nonexistent 'a0' STM32H7 chip
WasabiFan Sep 17, 2024
3614dc0
[stm32] Fix initialization of FDCAN message RAM
chris-durand Sep 24, 2024
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2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -166,7 +166,7 @@ Please [discover modm's peripheral drivers for your specific device][discover].
<td align="center">✅</td>
<td align="center">✅</td>
<td align="center">✅</td>
<td align="center">○</td>
<td align="center">✅</td>
<td align="center">✕</td>
<td align="center">✕</td>
<td align="center">✅</td>
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82 changes: 82 additions & 0 deletions examples/nucleo_h723zg/can/main.cpp
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@@ -0,0 +1,82 @@
/*
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* Copyright (c) 2020, Raphael Lehmann
*
* This file is part of the modm project.
*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/.
*/

#include <modm/board.hpp>
#include <modm/debug/logger.hpp>
#include <modm/board.hpp>

using namespace modm::literals;

// Set the log level
#undef MODM_LOG_LEVEL
#define MODM_LOG_LEVEL modm::log::INFO

int
main()
{
Board::initialize();

MODM_LOG_INFO << "CAN Test Program" << modm::endl;

MODM_LOG_INFO << "Initializing Fdcan1..." << modm::endl;
// Initialize Fdcan1
Fdcan1::connect<GpioA11::Rx, GpioA12::Tx>(Gpio::InputType::PullUp);
Fdcan1::initialize<Board::SystemClock, 125_kbps, 1_pct, 500_kbps>(9);

MODM_LOG_INFO << "Setting up Filter for Fdcan1..." << modm::endl;
// Receive every extended id message
Fdcan1::setExtendedFilter(0, Fdcan1::FilterConfig::Fifo0,
modm::can::ExtendedIdentifier(0),
modm::can::ExtendedMask(0));

MODM_LOG_INFO << "Initializing Fdcan2..." << modm::endl;
// Initialize Fdcan2
Fdcan2::connect<GpioB5::Rx, GpioB6::Tx>(Gpio::InputType::PullUp);
Fdcan2::initialize<Board::SystemClock, 125_kbps, 1_pct, 500_kbps>(12);

MODM_LOG_INFO << "Setting up Filter for Fdcan2..." << modm::endl;
// Receive every message
Fdcan2::setExtendedFilter(0, Fdcan2::FilterConfig::Fifo0,
modm::can::ExtendedIdentifier(0),
modm::can::ExtendedMask(0));

// Send a message
MODM_LOG_INFO << "Sending message on Fdcan1..." << modm::endl;
modm::can::Message msg1(1, 1);
msg1.setExtended(true);
msg1.data[0] = 0x11;
Fdcan1::sendMessage(msg1);

// Send a message
MODM_LOG_INFO << "Sending message on Fdcan2..." << modm::endl;
msg1.data[0] = 0x22;
Fdcan2::sendMessage(msg1);


while (true)
{
if (Fdcan1::isMessageAvailable())
{
MODM_LOG_INFO << "Fdcan1: Message is available..." << modm::endl;
modm::can::Message message;
Fdcan1::getMessage(message);
MODM_LOG_INFO << message << modm::endl;
}
if (Fdcan2::isMessageAvailable())
{
MODM_LOG_INFO << "Fdcan2: Message is available..." << modm::endl;
modm::can::Message message;
Fdcan2::getMessage(message);
MODM_LOG_INFO << message << modm::endl;
}
}

return 0;
}
13 changes: 13 additions & 0 deletions examples/nucleo_h723zg/can/project.xml
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@@ -0,0 +1,13 @@
<library>
<extends>modm:nucleo-h723zg</extends>
<options>
<option name="modm:build:build.path">../../../build/nucleo_h723zg/can</option>
</options>
<modules>
<module>modm:debug</module>
<module>modm:platform:can:1</module>
<module>modm:platform:can:2</module>
<module>modm:platform:can:3</module>
<module>modm:build:scons</module>
</modules>
</library>
21 changes: 19 additions & 2 deletions src/modm/board/nucleo_h723zg/board.hpp
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Expand Up @@ -30,9 +30,12 @@ using namespace modm::literals;
/// STM32H723ZG running at 550MHz from PLL clock generated from 8 MHz HSE
struct SystemClock
{
static constexpr uint32_t Hse = 8_MHz;

// Max 550MHz
static constexpr uint32_t SysClk = 550_MHz;
static constexpr uint32_t Pll1Q = SysClk / 4;
static constexpr uint32_t Pll2Q = 120_MHz;
// Max 550MHz
static constexpr uint32_t Hclk = SysClk / 1; // D1CPRE
static constexpr uint32_t Frequency = Hclk;
Expand Down Expand Up @@ -74,8 +77,9 @@ struct SystemClock

static constexpr uint32_t LpUart1 = Apb4;

static constexpr uint32_t Can1 = Apb1;
static constexpr uint32_t Can2 = Apb1;
static constexpr uint32_t Fdcan1 = Pll2Q;
static constexpr uint32_t Fdcan2 = Pll2Q;
static constexpr uint32_t Fdcan3 = Pll2Q;

static constexpr uint32_t I2c1 = Apb1;
static constexpr uint32_t I2c2 = Apb1;
Expand Down Expand Up @@ -122,6 +126,19 @@ struct SystemClock
.pllR = 2, // 550 MHz / 2 = 275 MHz
};
Rcc::enablePll1(Rcc::PllSource::Hse, pllFactors1);

// Use PLL2 for FDCAN 120MHz
const Rcc::PllFactors pllFactors2{
.range = Rcc::PllInputRange::MHz1_2,
.pllM = 4, // 8MHz / M= 2MHz
.pllN = 120, // 2MHz * N= 240MHz
.pllP = 2, // 240MHz / P= 120MHz
.pllQ = 2, // 240MHz / Q= 120MHz
.pllR = 2, // 240MHz / R= 120MHz
};
Rcc::enablePll2(Rcc::PllSource::ExternalClock, pllFactors2);
Rcc::setCanClockSource(Rcc::CanClockSource::Pll2Q);

// Use PLL3 for USB 48MHz
const Rcc::PllFactors pllFactors3{
.range = Rcc::PllInputRange::MHz4_8,
Expand Down
20 changes: 18 additions & 2 deletions src/modm/board/nucleo_h743zi/board.hpp
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Expand Up @@ -29,8 +29,11 @@ using namespace modm::literals;
/// STM32H743 running at 400MHz from the external 8MHz HSE
struct SystemClock
{
static constexpr uint32_t Hse = 8_MHz;

// NOTE: revision Y at 400MHz, only revision V runs at 480Mhz!!!
static constexpr uint32_t SysClk = 400_MHz;
static constexpr uint32_t Pll2Q = 120_MHz;
// Max 400MHz or 480MHz
static constexpr uint32_t Hclk = SysClk / 1; // D1CPRE
static constexpr uint32_t Frequency = Hclk;
Expand Down Expand Up @@ -70,8 +73,8 @@ struct SystemClock

static constexpr uint32_t LpUart1 = Apb4;

static constexpr uint32_t Can1 = Apb1;
static constexpr uint32_t Can2 = Apb1;
static constexpr uint32_t Fdcan1 = Pll2Q;
static constexpr uint32_t Fdcan2 = Pll2Q;

static constexpr uint32_t I2c1 = Apb1;
static constexpr uint32_t I2c2 = Apb1;
Expand Down Expand Up @@ -112,6 +115,19 @@ struct SystemClock
.pllR = 10, // 400MHz / R= 40MHz
};
Rcc::enablePll1(Rcc::PllSource::ExternalClock, pllFactors1);

// Use PLL2 for FDCAN 120MHz
const Rcc::PllFactors pllFactors2{
.range = Rcc::PllInputRange::MHz1_2,
.pllM = 4, // 8MHz / M= 2MHz
.pllN = 120, // 2MHz * N= 240MHz
.pllP = 2, // 240MHz / P= 120MHz
.pllQ = 2, // 240MHz / Q= 120MHz
.pllR = 2, // 240MHz / R= 120MHz
};
Rcc::enablePll2(Rcc::PllSource::ExternalClock, pllFactors2);
Rcc::setCanClockSource(Rcc::CanClockSource::Pll2Q);

// Use PLL3 for USB 48MHz
const Rcc::PllFactors pllFactors3{
.range = Rcc::PllInputRange::MHz4_8,
Expand Down
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