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Add STM32H7 support #652

Merged
merged 16 commits into from
Jul 15, 2021
Merged

Add STM32H7 support #652

merged 16 commits into from
Jul 15, 2021

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salkinium
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@salkinium salkinium commented Jul 6, 2021

Felt cute might merge later.
I'm testing in hardware on NUCLEO-H743ZI, which boots with a 64MHz HSI, so that's pretty fast.
Depends on modm-io/modm-devices#63.

  • Several corrections to modm-devices data regarding peripheral types
  • Fixup linkerscript .heapN/.data issues with RAM vs D1_SRAM{1-3} vs D2_SRAM{1-3} vs D3_SRAM
  • NUCLEO-H743ZI BSP with clock config for 400MHz
  • NUCLEO-H723ZI BSP with 550MHz clock
  • CI integration
  • Testing
  • Ignore dual-core devices for now
  • Fix RCC prescaler definitions
  • Fix Flash Latency
  • Fix SysTick at 550MHz. Running at 5Hz instead of 4Hz?
  • SysTick not /8 on revY, see errata
  • RCC Overdrive mode
  • RCC Apb3/4 Prescaler
  • RCC Pll implementation
  • RCC power plus initialization before SRAM access
  • Linkerscript refactoring

@salkinium salkinium added this to the 2021q3 milestone Jul 6, 2021
@salkinium salkinium mentioned this pull request Jul 6, 2021
@salkinium salkinium force-pushed the feature/stm32h7 branch 2 times, most recently from 5fe2c70 to 908f8f9 Compare July 7, 2021 00:24
@salkinium salkinium added the ci:hal Triggers the exhaustive HAL compile CI jobs label Jul 7, 2021
@salkinium salkinium added ci:hal Triggers the exhaustive HAL compile CI jobs and removed ci:hal Triggers the exhaustive HAL compile CI jobs labels Jul 7, 2021
@salkinium salkinium force-pushed the feature/stm32h7 branch 4 times, most recently from 288cc45 to 0c70400 Compare July 8, 2021 16:06
@salkinium salkinium added ci:hal Triggers the exhaustive HAL compile CI jobs and removed ci:hal Triggers the exhaustive HAL compile CI jobs labels Jul 8, 2021
@chris-durand
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chris-durand commented Jul 8, 2021

I have tested this on a Nucleo H723ZG and am trying to get the PLL to work. The RCC PLL implementation is not correct, but I expect to have a fix soon. The LED is blinking already at the right rate and I have uart output. I am currently adding settings for the APB3/4 prescaler.

The flash latency data is also not correct yet. For higher CPU frequencies the assertion always triggers that the frequency was not supported. And I get an assertion from the systick driver: "HLCK is too fast for the SysTick to run at 4Hz"

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salkinium commented Jul 8, 2021

Please wait, I've already fixed a bunch of stuff incl. inside modm-devices. The RCC implementation isn't from me and it's completely wrong for the PLL at least for my H743.

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And I get an assertion from the systick driver: "HLCK is too fast for the SysTick to run at 4Hz"

Yes, the fractional 32x32=64 multiplication overflows at ~536MHz and the H723 is running at 550MHz… When I implemented that the H7 only had the 480MHz devices… grrr

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I've pushed my fixes, but haven't tested the PLL config yet. Just so you're synced up.

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I've pushed my fixes, but haven't tested the PLL config yet. Just so you're synced up.

Thanks, I will look into it tomorrow. I noticed that in the H743 BSP the Apb* clocks are 240 MHz, the maximum is 120 MHz.

@salkinium salkinium force-pushed the feature/stm32h7 branch 2 times, most recently from fffc1b2 to 1df923a Compare July 9, 2021 01:07
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the Apb* clocks are 240 MHz, the maximum is 120 MHz.

Yup, had to look into the datasheet for that. ST's docs are a little crappy…

I can get my H743 up to 240MHz, so the PLL implementation is correct, however the µC crashes when I try 480MHz. I suspect my enableOverdriveMode() implementation, see Power Control -> Voltage Scaling in the RefMan, perhaps you can try on your board.

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I can get my H743 up to 240MHz, so the PLL implementation is correct, however the µC crashes when I try 480MHz. I suspect my enableOverdriveMode() implementation, see Power Control -> Voltage Scaling in the RefMan, perhaps you can try on your board.

Yes, same for me. Around 300 MHz was the maximum with default power settings.

I could get the H723 to run at 500 MHz with:

PWR->CR3 = PWR_CR3_LDOEN;
while(!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY));

PWR->D3CR &= ~PWR_D3CR_VOS;
while(!(PWR->D3CR & PWR_D3CR_VOSRDY));

It still hangs at 550 MHz. The overdrive bit does not exist for the H723.

I found a mistake in the RCC implementation, the Apb3 prescaler setting in the RCC driver configures the Apb4 prescaler:
apb4

The setting for Apb3 is in the D1 clock domain configuration register:

enum class
Apb3Prescaler : uint32_t
{
    Div1   = RCC_{{cfgr1}}_D1PPRE_DIV1,
    Div2   = RCC_{{cfgr1}}_D1PPRE_DIV2,
    Div4   = RCC_{{cfgr1}}_D1PPRE_DIV4,
    Div8   = RCC_{{cfgr1}}_D1PPRE_DIV8,
    Div16  = RCC_{{cfgr1}}_D1PPRE_DIV16
};

static inline bool
setApb3Prescaler(Apb3Prescaler prescaler)
{
	RCC->{{cfgr1}} = (RCC->{{cfgr1}} & ~RCC_{{cfgr1}}_D1PPRE) | uint32_t(prescaler);
	return true;
}

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According to the H723 reference manual we have to make sure no RAM is written until some power settings are configured:
h7_pwr

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The setting for Apb3 is in the D1 clock domain configuration register:

Oops, thanks! I'll fix it.

PWR->CR3 = PWR_CR3_LDOEN; while(!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY));

Ah, the internet said something about running from LDO, I'll check that.

I found this horror story: Migration from RevY to RevV for STM32H743/753 and STM32H750 Value line microcontrollers

Errata says the same thing

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According to the H723 reference manual we have to make sure no RAM is written until some power settings are configured:

Ok, then I'll put the LDO stuff into platform_startup.c.

@salkinium salkinium added the ci:hal Triggers the exhaustive HAL compile CI jobs label Jul 13, 2021
@salkinium salkinium added ci:hal Triggers the exhaustive HAL compile CI jobs and removed ci:hal Triggers the exhaustive HAL compile CI jobs labels Jul 13, 2021
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I made the mistake of looking into the Cortex-M7 Technical Reference Manual to figure out how the memory mapping works and thus tuned the linkerscripts again. I also added extensive documentation for STM32 and SAM.

@salkinium salkinium force-pushed the feature/stm32h7 branch 2 times, most recently from ab0d7f8 to 1620d5f Compare July 15, 2021 02:55
@salkinium salkinium added ci:hal Triggers the exhaustive HAL compile CI jobs and removed ci:hal Triggers the exhaustive HAL compile CI jobs labels Jul 15, 2021
chris-durand and others added 13 commits July 15, 2021 06:38
Add user-replaceable function modm_initialize_platform() called from
the reset handler. It will be executed after enabling internal memories
but before any memory initialization.
- Adds a generic linkerscript for all basic Cortex-M devices.
- Adds .data_{ram} and .noinit_{ram} sections to all memories.
- Uses MAX() to forward the heap location counter so that a very
  large .data section will collapse the heap to zero and "spill" into
  the next RAM section without overflowing the subsection SRAM1.
- Generalizes RAM heap section placement via macro.
Co-authored-by: Christopher Durand <christopher.durand@rwth-aachen.de>
Co-authored-by: Elias Rosch <elias@kiteswarms.com>
@salkinium salkinium added ci:hal Triggers the exhaustive HAL compile CI jobs and removed ci:hal Triggers the exhaustive HAL compile CI jobs labels Jul 15, 2021
@salkinium salkinium merged commit 80ed738 into modm-io:develop Jul 15, 2021
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Error generating documentation for device stm32h735zgt6: 'NoneType' object is not subscriptable

This again… LeSigh™

@salkinium salkinium deleted the feature/stm32h7 branch July 15, 2021 15:41
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