Bug fixes to SPI host, update regfiles and Bender (lowRISC#1)

* vendor: Update to using Bender 0.27.0 * vendor: Fixes to spi_host * makefile: Fix vendor command * vendor: Update generated regfiles Co-authored-by: Christopher Reinwardt <creinwar@ethz.ch>
mosaic-soc · Jan 23, 2023 · 881f8bc · 881f8bc
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diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -29,8 +29,8 @@ jobs:
       - name: Check generated sources
         run: make check_generated
 
-  check-import:
-    name: Check imported sources
+  check-vendor:
+    name: Check vendored sources
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v3
@@ -40,8 +40,8 @@ jobs:
           cache: pip
       - name: Python Requirements
         run: pip install -r requirements.txt
-      - name: Check import
-        run: make check_import
+      - name: Check vendor
+        run: make check_vendor
 
   check-license:
     name: Check license

diff --git a/Bender.yml b/Bender.yml
@@ -10,9 +10,9 @@ package:
 
 dependencies:
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.25.0 }
-  register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.3 }
+  register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 }
 
-external_import:
+vendor_package:
   - name: lowrisc_opentitan
     target_dir: src
     upstream: { git: "https://github.com/lowRISC/opentitan.git", rev: "726718a6de32aa047a4064e02e7b619699f054ed" }

diff --git a/Makefile b/Makefile
@@ -12,7 +12,7 @@ clean:
 	rm -f Bender.lock
 
 bender:
-	curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init | bash -s -- 0.26.0
+	curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init | bash -s -- 0.27.0
 	touch bender
 
 # Generate peripheral RTL
@@ -32,9 +32,9 @@ check_generated:
 	$(MAKE) -B otp
 	$(CHECK_CLEAN)
 
-check_import: bender
-	./bender import --refetch
+check_vendor: bender
+	./bender vendor init
 	$(CHECK_CLEAN)
 
 check: check_generated
-check: check_import
+check: check_vendor
diff --git a/README.md b/README.md
@@ -7,7 +7,7 @@ A selection of peripherals from lowRISC's [OpenTitan](https://github.com/lowRISC
 * Dependency and IP management using [Bender](https://github.com/pulp-platform/bender).
 * Minor functional fixes and changes.
 
-This repository uses Bender's `import` command to fully include the remote code in `src` and apply the patches included in `patches`. The IP RTL is pregenerated in its standard configuration, but can be reconfigured in the including project.
+This repository uses Bender's `vendor` command to fully include the remote code in `src` and apply the patches included in `patches`. The IP RTL is pregenerated in its standard configuration, but can be reconfigured in the including project.
 
 ## Reconfiguring IPs
 
@@ -32,13 +32,13 @@ all: otp
 After making uncommitted changes to the forked IPs, you can generate a patch for them with:
 
 ```
-bender import --gen_patch
+bender vendor --gen_patch
 ```
 
 Then rename the generated file to `<next_index>_<patch_description>.patch`. To verify correct patch application:
 
 ```
-make check_import
+make check_vendor
 ```
 
 ## Licensing

diff --git a/patches/gpio/0002-vendor-Update-generated-regfiles.patch b/patches/gpio/0002-vendor-Update-generated-regfiles.patch
@@ -0,0 +1,90 @@
+From 13ac273ddbdd5ce55b44571dca29a0afad172502 Mon Sep 17 00:00:00 2001
+From: Paul Scheffler <paulsc@iis.ee.ethz.ch>
+Date: Mon, 23 Jan 2023 13:33:22 +0100
+Subject: [PATCH] vendor: Update generated regfiles
+
+---
+ rtl/gpio_reg_top.sv | 62 ++++++++++++++++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 57 insertions(+), 5 deletions(-)
+
+diff --git a/rtl/gpio_reg_top.sv b/rtl/gpio_reg_top.sv
+index ec6fb5401..b6e54d6f9 100644
+--- a/rtl/gpio_reg_top.sv
++++ b/rtl/gpio_reg_top.sv
+@@ -8,12 +8,12 @@
+ `include "common_cells/assertions.svh"
+
+ module gpio_reg_top #(
+-    parameter type reg_req_t = logic,
+-    parameter type reg_rsp_t = logic,
+-    parameter int AW = 6
++  parameter type reg_req_t = logic,
++  parameter type reg_rsp_t = logic,
++  parameter int AW = 6
+ ) (
+-  input clk_i,
+-  input rst_ni,
++  input logic clk_i,
++  input logic rst_ni,
+   input  reg_req_t reg_req_i,
+   output reg_rsp_t reg_rsp_o,
+   // To HW
+@@ -741,3 +741,55 @@ module gpio_reg_top #(
+   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+ endmodule
++
++module gpio_reg_top_intf
++#(
++  parameter int AW = 6,
++  localparam int DW = 32
++) (
++  input logic clk_i,
++  input logic rst_ni,
++  REG_BUS.in  regbus_slave,
++  // To HW
++  output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write
++  input  gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read
++  // Config
++  input devmode_i // If 1, explicit error return for unmapped register access
++);
++ localparam int unsigned STRB_WIDTH = DW/8;
++
++`include "register_interface/typedef.svh"
++`include "register_interface/assign.svh"
++
++  // Define structs for reg_bus
++  typedef logic [AW-1:0] addr_t;
++  typedef logic [DW-1:0] data_t;
++  typedef logic [STRB_WIDTH-1:0] strb_t;
++  `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)
++
++  reg_bus_req_t s_reg_req;
++  reg_bus_rsp_t s_reg_rsp;
++  
++  // Assign SV interface to structs
++  `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
++  `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
++
++  
++
++  gpio_reg_top #(
++    .reg_req_t(reg_bus_req_t),
++    .reg_rsp_t(reg_bus_rsp_t),
++    .AW(AW)
++  ) i_regs (
++    .clk_i,
++    .rst_ni,
++    .reg_req_i(s_reg_req),
++    .reg_rsp_o(s_reg_rsp),
++    .reg2hw, // Write
++    .hw2reg, // Read
++    .devmode_i
++  );
++  
++endmodule
++
++
+-- 
+2.16.5
+
diff --git a/patches/i2c/0002-vendor-Update-generated-regfiles.patch b/patches/i2c/0002-vendor-Update-generated-regfiles.patch
@@ -0,0 +1,90 @@
+From 0fde4abb3750bda19ff3b121adffb8f773c3bda7 Mon Sep 17 00:00:00 2001
+From: Paul Scheffler <paulsc@iis.ee.ethz.ch>
+Date: Mon, 23 Jan 2023 13:34:11 +0100
+Subject: [PATCH] vendor: Update generated regfiles
+
+---
+ rtl/i2c_reg_top.sv | 62 +++++++++++++++++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 57 insertions(+), 5 deletions(-)
+
+diff --git a/rtl/i2c_reg_top.sv b/rtl/i2c_reg_top.sv
+index 341876e99..8606a4929 100644
+--- a/rtl/i2c_reg_top.sv
++++ b/rtl/i2c_reg_top.sv
+@@ -8,12 +8,12 @@
+ `include "common_cells/assertions.svh"
+
+ module i2c_reg_top #(
+-    parameter type reg_req_t = logic,
+-    parameter type reg_rsp_t = logic,
+-    parameter int AW = 7
++  parameter type reg_req_t = logic,
++  parameter type reg_rsp_t = logic,
++  parameter int AW = 7
+ ) (
+-  input clk_i,
+-  input rst_ni,
++  input logic clk_i,
++  input logic rst_ni,
+   input  reg_req_t reg_req_i,
+   output reg_rsp_t reg_rsp_o,
+   // To HW
+@@ -3355,3 +3355,55 @@ module i2c_reg_top #(
+   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+ endmodule
++
++module i2c_reg_top_intf
++#(
++  parameter int AW = 7,
++  localparam int DW = 32
++) (
++  input logic clk_i,
++  input logic rst_ni,
++  REG_BUS.in  regbus_slave,
++  // To HW
++  output i2c_reg_pkg::i2c_reg2hw_t reg2hw, // Write
++  input  i2c_reg_pkg::i2c_hw2reg_t hw2reg, // Read
++  // Config
++  input devmode_i // If 1, explicit error return for unmapped register access
++);
++ localparam int unsigned STRB_WIDTH = DW/8;
++
++`include "register_interface/typedef.svh"
++`include "register_interface/assign.svh"
++
++  // Define structs for reg_bus
++  typedef logic [AW-1:0] addr_t;
++  typedef logic [DW-1:0] data_t;
++  typedef logic [STRB_WIDTH-1:0] strb_t;
++  `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)
++
++  reg_bus_req_t s_reg_req;
++  reg_bus_rsp_t s_reg_rsp;
++  
++  // Assign SV interface to structs
++  `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
++  `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
++
++  
++
++  i2c_reg_top #(
++    .reg_req_t(reg_bus_req_t),
++    .reg_rsp_t(reg_bus_rsp_t),
++    .AW(AW)
++  ) i_regs (
++    .clk_i,
++    .rst_ni,
++    .reg_req_i(s_reg_req),
++    .reg_rsp_o(s_reg_rsp),
++    .reg2hw, // Write
++    .hw2reg, // Read
++    .devmode_i
++  );
++  
++endmodule
++
++
+-- 
+2.16.5
+
diff --git a/patches/rv_plic/0003-vendor-Update-generated-regfiles.patch b/patches/rv_plic/0003-vendor-Update-generated-regfiles.patch
@@ -0,0 +1,90 @@
+From 5ac0d748f4a0d417fd884c25e93a8fb51fc6cddb Mon Sep 17 00:00:00 2001
+From: Paul Scheffler <paulsc@iis.ee.ethz.ch>
+Date: Mon, 23 Jan 2023 13:34:41 +0100
+Subject: [PATCH] vendor:	Update generated regfiles
+
+---
+ rtl/rv_plic_reg_top.sv | 62 ++++++++++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 57 insertions(+), 5 deletions(-)
+
+diff --git a/rtl/rv_plic_reg_top.sv b/rtl/rv_plic_reg_top.sv
+index 6647b9ae8..410c61c3c 100644
+--- a/rtl/rv_plic_reg_top.sv
++++ b/rtl/rv_plic_reg_top.sv
+@@ -8,12 +8,12 @@
+ `include "common_cells/assertions.svh"
+
+ module rv_plic_reg_top #(
+-    parameter type reg_req_t = logic,
+-    parameter type reg_rsp_t = logic,
+-    parameter int AW = 22
++  parameter type reg_req_t = logic,
++  parameter type reg_rsp_t = logic,
++  parameter int AW = 22
+ ) (
+-  input clk_i,
+-  input rst_ni,
++  input logic clk_i,
++  input logic rst_ni,
+   input  reg_req_t reg_req_i,
+   output reg_rsp_t reg_rsp_o,
+   // To HW
+@@ -4496,3 +4496,55 @@ module rv_plic_reg_top #(
+   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+ endmodule
++
++module rv_plic_reg_top_intf
++#(
++  parameter int AW = 22,
++  localparam int DW = 32
++) (
++  input logic clk_i,
++  input logic rst_ni,
++  REG_BUS.in  regbus_slave,
++  // To HW
++  output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
++  input  rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read
++  // Config
++  input devmode_i // If 1, explicit error return for unmapped register access
++);
++ localparam int unsigned STRB_WIDTH = DW/8;
++
++`include "register_interface/typedef.svh"
++`include "register_interface/assign.svh"
++
++  // Define structs for reg_bus
++  typedef logic [AW-1:0] addr_t;
++  typedef logic [DW-1:0] data_t;
++  typedef logic [STRB_WIDTH-1:0] strb_t;
++  `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)
++
++  reg_bus_req_t s_reg_req;
++  reg_bus_rsp_t s_reg_rsp;
++  
++  // Assign SV interface to structs
++  `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
++  `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
++
++  
++
++  rv_plic_reg_top #(
++    .reg_req_t(reg_bus_req_t),
++    .reg_rsp_t(reg_bus_rsp_t),
++    .AW(AW)
++  ) i_regs (
++    .clk_i,
++    .rst_ni,
++    .reg_req_i(s_reg_req),
++    .reg_rsp_o(s_reg_rsp),
++    .reg2hw, // Write
++    .hw2reg, // Read
++    .devmode_i
++  );
++  
++endmodule
++
++
+-- 
+2.16.5
+
diff --git a/patches/spi_host/0002-vendor-Fixes-to-spi_host.patch b/patches/spi_host/0002-vendor-Fixes-to-spi_host.patch
@@ -0,0 +1,39 @@
+From 55ab322b3120cfe453bb1a444870e9cc9a8b128d Mon Sep 17 00:00:00 2001
+From: Christopher Reinwardt <creinwar@ethz.ch>
+Date: Mon, 23 Jan 2023 13:06:53 +0100
+Subject: [PATCH] vendor: Fixes to spi_host
+
+---
+ rtl/spi_host_byte_merge.sv | 2 +-
+ rtl/spi_host_fsm.sv        | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/rtl/spi_host_byte_merge.sv b/rtl/spi_host_byte_merge.sv
+index bc9cd0121..ef7114160 100644
+--- a/rtl/spi_host_byte_merge.sv
++++ b/rtl/spi_host_byte_merge.sv
+@@ -54,7 +54,7 @@ module spi_host_byte_merge (
+     .clk_i,
+     .rst_ni,
+     .clr_i    (clr),
+-    .wdata_i  (byte_i),
++    .wdata_i  (do_fill ? '0 : byte_i),
+     .wvalid_i (byte_valid),
+     .wready_o (byte_ready),
+     .rdata_o  (word_o),
+diff --git a/rtl/spi_host_fsm.sv b/rtl/spi_host_fsm.sv
+index 3e01bff99..e0106374e 100644
+--- a/rtl/spi_host_fsm.sv
++++ b/rtl/spi_host_fsm.sv
+@@ -487,7 +487,7 @@ module spi_host_fsm
+   assign speed_o           = cmd_speed;
+   assign sample_en_d       = byte_starting | shift_en_o;
+   assign full_cyc_o        = full_cyc;
+-  assign cmd_end_o         = (byte_cntr_q == 'h1) & wr_en_o & sr_wr_ready_i;
++  assign cmd_end_o         = ((byte_cntr_q == 'h1) & wr_en_o & ~rd_en_o & sr_wr_ready_i) || ((byte_cntr_q == 'h0) & rd_en_o & sr_rd_ready_i);
+
+   always_ff @(posedge clk_i or negedge rst_ni) begin
+     if (!rst_ni) begin
+-- 
+2.16.5
+