tracer: Update tracer to the multiprotocol version of iDMA (#8)

* Add a tracer for the DMA #8

Bender.yml

@@ -19,6 +19,7 @@ dependencies:
 
 export_include_dirs:
   - src/include
+  - target/rtl/include
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this

idma.mk

@@ -68,9 +68,11 @@ IDMA_GEN        := $(IDMA_UTIL_DIR)/gen_idma.py
 IDMA_GEN_SRC    := $(IDMA_UTIL_DIR)/mario/backend.py \
 				   $(IDMA_UTIL_DIR)/mario/bender.py \
 				   $(IDMA_UTIL_DIR)/mario/database.py \
+				   $(IDMA_UTIL_DIR)/mario/frontend.py \
 				   $(IDMA_UTIL_DIR)/mario/legalizer.py \
 				   $(IDMA_UTIL_DIR)/mario/synth.py \
 				   $(IDMA_UTIL_DIR)/mario/testbench.py \
+				   $(IDMA_UTIL_DIR)/mario/tracer.py \
 				   $(IDMA_UTIL_DIR)/mario/transport_layer.py \
 				   $(IDMA_UTIL_DIR)/mario/util.py \
 				   $(IDMA_UTIL_DIR)/mario/wave.py
@@ -112,12 +114,18 @@ $(IDMA_RTL_DIR)/tb_idma_backend_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_backend_%
 $(IDMA_VSIM_DIR)/wave/backend_%.do: $(IDMA_GEN) $(IDMA_RTL_DIR)/tb_idma_backend_%.sv $(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl
 	$(call idma_gen,vsim_wave,$(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl,$(IDMA_DB_FILES),$*,,$@)
 
+$(IDMA_RTL_DIR)/include/idma/tracer.svh: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/include/idma/tpl/tracer.svh.tpl $(IDMA_DB_FILES) $(IDMA_ROOT)/idma.mk
+	mkdir -p $(IDMA_RTL_DIR)/include/idma
+	$(call idma_gen,tracer,$(IDMA_ROOT)/src/include/idma/tpl/tracer.svh.tpl,$(IDMA_DB_FILES),$(IDMA_BACKEND_IDS),$(IDMA_FE_IDS),$@)
+
 idma_rtl_clean:
 	rm -f $(IDMA_RTL_DIR)/Bender.yml
 	rm -f $(IDMA_RTL_DIR)/*.sv
 	rm -f $(IDMA_VSIM_DIR)/wave/*.do
+	rm -f $(IDMA_RTL_DIR)/include/idma/tracer.svh
 
 # assemble the required files
+IDMA_RTL_ALL += $(IDMA_RTL_DIR)/include/idma/tracer.svh
 IDMA_RTL_ALL += $(foreach X,$(IDMA_RTL_FILES),$(foreach Y,$(IDMA_BACKEND_IDS),$X_$Y.sv))
 IDMA_TB_ALL  += $(foreach Y,$(IDMA_BACKEND_IDS),$(IDMA_RTL_DIR)/tb_idma_backend_$Y.sv)
 IDMA_TB_ALL  += $(foreach Y,$(IDMA_BACKEND_IDS),$(IDMA_VSIM_DIR)/wave/backend_$Y.do)
@@ -263,12 +271,12 @@ idma_sim_clean:
 	rm -f  $(IDMA_VSIM_DIR)/dma_transfers.txt
 	rm -f  $(IDMA_VSIM_DIR)/transcript
 	rm -f  $(IDMA_VSIM_DIR)/wlf*
-	rm -f  $(IDMA_VSIM_DIR)/logs/wlf*
-	rm -f  $(IDMA_VSIM_DIR)/logs/*.wlf
+	rm -f  $(IDMA_VSIM_DIR)/*.wlf
 	rm -f  $(IDMA_VSIM_DIR)/*.vstf
 	rm -f  $(IDMA_VSIM_DIR)/*.vcd
 	rm -f  $(IDMA_VSIM_DIR)/modelsim.ini
-	rm -f  $(IDMA_VSIM_DIR)/logs/*vsim.log
+	rm -f  $(IDMA_VSIM_DIR)/*.log
+	rm -f  $(IDMA_VSIM_DIR)/*.txt
 
 
 # --------------
@@ -312,7 +320,8 @@ idma_vcs_clean:
 	rm -rf $(IDMA_VCS_DIR)/bin
 	rm -f  $(IDMA_VCS_DIR)/ucli.key
 	rm -f  $(IDMA_VCS_DIR)/vc_hdrs.h
-	rm -f  $(IDMA_VCS_DIR)/logs/*.vcs.log
+	rm -f  $(IDMA_VCS_DIR)/*.log
+	rm -f  $(IDMA_VCS_DIR)/*.txt
 
 
 # --------------
@@ -346,6 +355,22 @@ idma_verilator_clean:
 	rm -rf $(IDMA_VLT_DIR)
 
 
+# ---------------
+# Trace
+# ---------------
+
+.PHONY: idma_trace_clean
+
+IDMA_TRACE := $(IDMA_UTIL_DIR)/trace_idma.py
+
+%_trace.rpt: $(IDMA_TRACE) $(IDMA_DB_FILES) %.txt
+	$(PYTHON) $(IDMA_TRACE) --db $(IDMA_DB_FILES) --trace $*.txt > $@
+
+idma_trace_clean:
+	rm -f $(IDMA_VSIM_DIR)/*_trace.rpt
+	rm -f $(IDMA_VCS_DIR)/*_trace.rpt
+
+
 # ---------------
 # Doc
 # ---------------
@@ -385,7 +410,7 @@ idma_nonfree_clean:
 
 .PHONY: idma_clean_all idma_clean idma_misc_clean
 
-idma_clean_all idma_clean: idma_rtl_clean idma_reg_clean idma_morty_clean idma_sim_clean idma_vcs_clean idma_verilator_clean idma_spinx_doc_clean
+idma_clean_all idma_clean: idma_rtl_clean idma_reg_clean idma_morty_clean idma_sim_clean idma_vcs_clean idma_verilator_clean idma_spinx_doc_clean idma_trace_clean
 
 idma_misc_clean:
 	rm -rf scripts/__pycache__

requirements.txt

@@ -8,3 +8,4 @@ sphinx-rtd-theme
 recommonmark
 sphinxcontrib-svg2pdfconverter
 pylint
+flatdict

src/db/idma_axi.yml

@@ -224,3 +224,13 @@ synth_wrapper_assign_read: |
     assign axi_read_rsp.r.last   = axi_r_last_i;
     assign axi_read_rsp.r.user   = axi_r_user_i;
     assign axi_read_rsp.r_valid  = axi_r_valid_i;
+trace_signals:
+    read:
+        rsp:
+            valid: axi_read_rsp_i.r_valid
+            ready: axi_read_req_o.r_ready
+    write:
+        req:
+            valid: axi_write_req_o.w_valid
+            ready: axi_write_rsp_i.w_ready
+            strobe: axi_write_req_o.w.strb

src/db/idma_axi_lite.yml

@@ -157,3 +157,13 @@ synth_wrapper_assign_read: |
     assign axi_lite_read_rsp.r.data    = axi_lite_r_data_i;
     assign axi_lite_read_rsp.r.resp    = axi_lite_r_resp_i;
     assign axi_lite_read_rsp.r_valid   = axi_lite_r_valid_i;
+trace_signals:
+    read:
+        rsp:
+            valid: axi_lite_read_rsp_i.r_valid
+            ready: axi_lite_read_req_o.r_ready
+    write:
+        req:
+            valid: axi_lite_write_req_o.w_valid
+            ready: axi_lite_write_rsp_i.w_ready
+            strobe: axi_lite_write_req_o.w.strb

src/db/idma_axi_stream.yml

@@ -320,3 +320,14 @@ synth_wrapper_assign_write: |
     assign axi_stream_write_tvalid_o = axi_stream_write_req.tvalid;
 
     assign axi_stream_write_rsp.tready = axi_stream_write_tready_i;
+trace_signals:
+    read:
+        rsp:
+            valid: axi_stream_read_rsp_i.tvalid
+            ready: axi_stream_read_req_o.tready
+            strobe: axi_stream_read_rsp_i.t.strb
+    write:
+        req:
+            valid: axi_stream_write_req_o.tvalid
+            ready: axi_stream_write_rsp_i.tready
+            strobe: axi_stream_write_req_o.t.strb

src/db/idma_init.yml

@@ -100,3 +100,12 @@ synth_wrapper_assign_read: |
     assign init_read_rsp.rsp_valid           = init_read_rsp_valid_i;
     assign init_read_rsp.rsp_chan.init_value = init_read_rsp_init_value_i;
     assign init_read_rsp_ready_o             = init_read_req.rsp_ready;
+trace_signals:
+    read:
+        req:
+            valid: init_read_req_o.req_valid
+            config: init_read_req_o.req_chan.cfg
+            ready: init_read_rsp_i.req_ready
+        rsp:
+            valid: init_read_rsp_i.rsp_valid
+            ready: init_read_req_o.rsp_ready

src/db/idma_obi.yml

@@ -161,3 +161,14 @@ synth_wrapper_assign_read: |
     assign obi_read_rsp.r_valid = obi_read_rsp_r_valid_i;
     assign obi_read_rsp.r.rdata = obi_read_rsp_r_rdata_i;
     assign obi_read_rsp.r.rid   = obi_read_rsp_r_rid_i;
+trace_signals:
+    read:
+        rsp:
+            valid: obi_read_req_o.r_valid
+            ready: obi_read_rsp_i.r_ready
+    write:
+        req:
+            valid: obi_write_req_o.a_req
+            ready: obi_write_rsp_i.a_gnt
+            strobe: obi_write_req_o.a.be
+            write_en: obi_write_req_o.a.we

src/db/idma_tilelink.yml

@@ -241,3 +241,13 @@ synth_wrapper_assign_read: |
     assign tilelink_read_rsp.d.denied  = tilelink_read_rsp_d_denied_i;
     assign tilelink_read_rsp.d.data    = tilelink_read_rsp_d_data_i;
     assign tilelink_read_rsp.d.corrupt = tilelink_read_rsp_d_corrupt_i;
+trace_signals:
+    read:
+        rsp:
+            valid: tilelink_read_rsp_i.d_valid
+            ready: tilelink_read_req_o.d_ready
+    write:
+        req:
+            valid: tilelink_write_req_o.a_valid
+            ready: tilelink_write_rsp_i.a_ready
+            strobe: tilelink_write_req_o.a.mask

src/include/idma/tpl/tracer.svh.tpl

@@ -0,0 +1,30 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Authors:
+// - Thomas Benz <tbenz@ethz.ch>
+
+// Macro holding all the resources for the iDMA backend tracer
+`ifndef IDMA_TRACER_SVH_
+`define IDMA_TRACER_SVH_
+
+// largest type to trace
+`define IDMA_TRACER_MAX_TYPE_WIDTH 1024
+`define IDMA_TRACER_MAX_TYPE logic [`IDMA_TRACER_MAX_TYPE_WIDTH-1:0]
+
+// string assembly function
+`define IDMA_TRACER_STR_ASSEMBLY(__dict, __cond) <%text>\</%text>
+    if(__cond) begin <%text>\</%text>
+        trace = $sformatf("%s'%s':{", trace, `"__dict`"); <%text>\</%text>
+        foreach(__dict``[key]) trace = $sformatf("%s'%s': 0x%0x,", trace, key, __dict``[key]); <%text>\</%text>
+        trace = $sformatf("%s},", trace); <%text>\</%text>
+    end
+
+// helper to clear a condition
+`define IDMA_TRACER_CLEAR_COND(__cond) <%text>\</%text>
+    if(__cond) begin <%text>\</%text>
+        __cond = ~__cond; <%text>\</%text>
+    end
+${body}
+`endif

target/rtl/.gitignore

@@ -1,3 +1,4 @@
 Bender.yml
+include
 *.sv
 *.hjson

target/rtl/tpl/Bender.yml.tpl

@@ -16,6 +16,7 @@ dependencies:
 export_include_dirs:
   - ../../src/include
   - ../../test
+  - include
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this