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[WIP] building externals for android #63

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@umlaeute umlaeute commented Mar 9, 2020

this is really just a blind-flight attempt on building externals for android.

Related: #60

compilation

basic flags and quirks have been backported from the original template-Makefile.
The notable omission is that there is no override for the sysroot.

compilation has been tested on dockcross/android-arm and dockcross/android-arm64 (docker-images for cross-compilation).

i have no idea how to target specific android releases with dockcross.

i also have no idea whether this would also work with a normal installation of the NDK.

testing

building has been tested.

but since the build-environment is just a cross-builder, no runtime tests have been performed yet.

compiles on dockcross/android-arm and dockcross/android-arm64
not runtime tests have been performed yet (as i only have a cross-compilation environment)

Related: #60
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umlaeute commented Mar 9, 2020

since @claudeha has requested this feature, probably he can do some real world tests

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umlaeute commented Mar 9, 2020

actually, i just noticed that it doesn't work at all yet :-(

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umlaeute commented Mar 9, 2020

the problems being obviously, that on androind we need to do a bit of mangling to get the output name.

  • extension is .so
  • file-prefix is lib (mandatory)
  • ~ is replaced by _tilde.

e.g. foo~.c compiles to libfoo_tilde.so.

However, link-class assumes that the final executable-name can be constructed by simply appending `.$(extension), see

define link-class
$(compile-$1) \
$($1.ldflags) $($2.class.ldflags) \
-o $2.$(extension) \
$(addsuffix .o, $(basename $($2.class.sources))) \
$(addsuffix .o, $(basename $(common.sources))) \
$($1.ldlibs) $($2.class.ldlibs) $(shared.lib)
endef

@katjav any ideas how you would want to solve this?

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katjav commented Mar 10, 2020

It seems for Android the class names should be manipulated to get the desired output names. There is no strict relation required between source file name and class name. Class binaries may be built from multiple input files as well. A lib makefile could for example define:

foo~.class.sources = bar.c baz.c

All variables under class.sources are evaluated to this form as well. For example, when a lib makefile defines:

class.sources = foo.c bar.c

this will be translated to:

foo.class.sources = foo.c
bar.class.sources = bar.c

Line 720 is the point where all *.class.sources are known, mangling could be done directly thereafter.

define add-class-source
$(notdir $(basename $v)).class.sources += $v
endef
$(foreach v, $(class.sources), $(eval $(add-class-source)))
# derive class names from <classname>.class.sources variables
sourcevariables := $(filter %.class.sources, $(.VARIABLES))
classes := $(basename $(basename $(sourcevariables)))

Not sure if such an approach may have undesired side effects. Also I wonder how this issue was avoided in the Makefile template?

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