Add _mm_loadu_si64

crates/core_arch/src/x86/sse.rs

@@ -1251,6 +1251,19 @@ pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
     simd_shuffle4(a, a, [3, 2, 1, 0])
 }
 
+/// Loads unaligned 64-bits of integer data from memory into new vector.
+///
+/// `mem_addr` does not need to be aligned on any particular boundary.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_si64)
+#[inline]
+#[target_feature(enable = "sse")]
+#[cfg_attr(test, assert_instr(movq))]
+#[stable(feature = "simd_x86_mm_loadu_si64", since = "1.46.0")]
+pub unsafe fn _mm_loadu_si64(mem_addr: *const u8) -> __m128i {
+    _mm_set_epi64x(ptr::read_unaligned(mem_addr as *const i64), 0)
+}
+
 /// Stores the upper half of `a` (64 bits) into memory.
 ///
 /// This intrinsic corresponds to the `MOVHPS` instruction. The compiler may
@@ -3658,6 +3671,13 @@ mod tests {
         assert_eq_m128(r, e);
     }
 
+    #[simd_test(enable = "sse2")]
+    unsafe fn test_mm_loadu_si64() {
+        let a = _mm_setr_epi64x(5, 6);
+        let r = _mm_loadu_si64(&a as *const _ as *const _);
+        assert_eq_m128i(r, _mm_set_epi64x(5, 0));
+    }
+
     #[simd_test(enable = "sse")]
     unsafe fn test_mm_storeh_pi() {
         let mut vals = [0.0f32; 8];