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Merge pull request #489 from sifive/u8-delay
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U8 initial support
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@bsousi5
bsousi5 authored May 14, 2020
2 parents 4853a1e + b318a75 commit 29d6f85
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Showing 13 changed files with 43 additions and 14 deletions.
3 changes: 2 additions & 1 deletion bsp/freedom-e310-arty/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = sifive-3-series
TARGET_TAGS = board openocd
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/qemu-sifive-e31/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = None
TARGET_TAGS = qemu
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/qemu-sifive-s51/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = None
TARGET_TAGS = qemu
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/qemu-sifive-u54/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = None
TARGET_TAGS = qemu
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/qemu-sifive-u54mc/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = None
TARGET_TAGS = qemu
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/sifive-hifive-unleashed/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = sifive-5-series
TARGET_TAGS = board openocd
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/sifive-hifive1-revb/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = sifive-3-series
TARGET_TAGS = board jlink
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/sifive-hifive1/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = sifive-3-series
TARGET_TAGS = board openocd
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
3 changes: 2 additions & 1 deletion bsp/spike/settings.mk
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Expand Up @@ -9,4 +9,5 @@ RISCV_SERIES = None
TARGET_TAGS = spike
TARGET_DHRY_ITERS = 20000000
TARGET_CORE_ITERS = 5000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_FREERTOS_WAIT_MS = 1000
TARGET_INTR_WAIT_CYCLE = 0
2 changes: 1 addition & 1 deletion scripts/esdk-settings-generator
Submodule esdk-settings-generator updated 1 files
+9 −3 generate_settings.py
22 changes: 21 additions & 1 deletion scripts/standalone.mk
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Expand Up @@ -153,8 +153,18 @@ RISCV_CFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=$(RISCV_CMOD
RISCV_CXXFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=$(RISCV_CMODEL)
RISCV_ASFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=$(RISCV_CMODEL)
# Prune unused functions and data
ifeq ($(RISCV_SERIES),sifive-8-series)
ifeq ($(PROGRAM),dhrystone)
RISCV_CFLAGS += -fno-function-sections -fno-data-sections
RISCV_CXXFLAGS += -fno-function-sections -fno-data-sections
else
RISCV_CFLAGS += -ffunction-sections -fdata-sections
RISCV_CXXFLAGS += -ffunction-sections -fdata-sections
endif
else
RISCV_CFLAGS += -ffunction-sections -fdata-sections
RISCV_CXXFLAGS += -ffunction-sections -fdata-sections
endif
# Include the Metal headers
RISCV_CCASFLAGS += -I$(abspath $(BSP_DIR)/install/include/)
RISCV_CFLAGS += -I$(abspath $(BSP_DIR)/install/include/)
Expand Down Expand Up @@ -204,15 +214,22 @@ RISCV_XCFLAGS += -DDHRY_ITERS=$(TARGET_DHRY_ITERS)
endif

ifeq ($(PROGRAM),coremark)
ifeq ($(RISCV_SERIES),sifive-8-series)
# 8-series currently uses 7-series mtune, but this may change
RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -funroll-all-loops --param max-inline-insns-auto=20 -falign-functions=8 -falign-jumps=8 -falign-loops=8 --param inline-min-speedup=10 -mtune=sifive-7-series -ffast-math
endif
ifeq ($(RISCV_SERIES),sifive-7-series)
RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -funroll-all-loops --param max-inline-insns-auto=20 -falign-functions=8 -falign-jumps=8 -falign-loops=8 --param inline-min-speedup=10 -mtune=sifive-7-series -ffast-math
else
endif
ifneq ($(RISCV_SERIES),sifive-8-series)
ifneq ($(RISCV_SERIES),sifive-7-series)
ifeq ($(RISCV_XLEN),32)
RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -falign-functions=16 -falign-jumps=4 -falign-loops=4 -finline-limit=1000 -fno-if-conversion2 -fselective-scheduling -fno-tree-dominator-opts -fno-reg-struct-return -fno-rename-registers --param case-values-threshold=8 -fno-crossjumping -freorder-blocks-and-partition -fno-tree-loop-if-convert -fno-tree-sink -fgcse-sm -fno-strict-overflow
else
RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -falign-functions=16 -falign-jumps=4 -falign-loops=4 -finline-limit=1000 -fno-if-conversion2 -fselective-scheduling -fno-tree-dominator-opts
endif
endif
endif
RISCV_XCFLAGS += -DITERATIONS=$(TARGET_CORE_ITERS)
endif

Expand All @@ -224,6 +241,9 @@ ifneq ($(filter rtl,$(TARGET_TAGS)),)
RISCV_XCFLAGS += -DHCA_BYPASS_TRNG
endif

# A method to pass cycle delay
RISCV_XCFLAGS += -DMETAL_WAIT_CYCLE=$(TARGET_INTR_WAIT_CYCLE)

#############################################################
# Software
#############################################################
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2 changes: 1 addition & 1 deletion software/software-interrupt
Submodule software-interrupt updated 2 files
+2 −0 Makefile
+8 −0 software-interrupt.c
4 changes: 2 additions & 2 deletions wit-manifest.json
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Expand Up @@ -35,7 +35,7 @@
"source": "git@github.com:sifive/openocdcfg-generator.git"
},
{
"commit": "e15884b71bbd8d562d1f5228e021c6b6c1201990",
"commit": "9728da6024564a8cb7df66baf70920c4ed5af4e0",
"name": "esdk-settings-generator",
"source": "git@github.com:sifive/esdk-settings-generator.git"
},
Expand Down Expand Up @@ -145,7 +145,7 @@
"source": "git@github.com:sifive/example-sifive-welcome.git"
},
{
"commit": "b10a32d2b079e8e454648bd605b49954ed0fd505",
"commit": "125c460addac602cd5b7d25960918cc0fd6a419a",
"name": "example-software-interrupt",
"source": "git@github.com:sifive/example-software-interrupt.git"
},
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