Spi Deref

CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Use `Deref` for SPI generic implementations instead of macros
+- Make traits `rcc::Enable` and `rcc::Reset` public, but `RccBus` sealed
 - Add `QeiOptions` struct to configure slave mode and auto reload value of QEI interface
 
 ## [v0.5.3] - 2020-01-20

examples/spi-dma.rs

@@ -41,7 +41,7 @@ fn main() -> ! {
         polarity: Polarity::IdleLow,
         phase: Phase::CaptureOnFirstTransition
     };
-    let mut spi = Spi::spi2(
+    let spi = Spi::spi2(
         dp.SPI2,
         pins,
         spi_mode,

src/i2c.rs

@@ -11,7 +11,7 @@ use crate::gpio::{Alternate, OpenDrain};
 use crate::hal::blocking::i2c::{Read, Write, WriteRead};
 use nb::Error::{Other, WouldBlock};
 use nb::{Error as NbError, Result as NbResult};
-use crate::rcc::{Clocks, APB1, Enable, Reset, RccBus, GetBusFreq};
+use crate::rcc::{Clocks, Enable, Reset, sealed::RccBus, GetBusFreq};
 use crate::pac::{DWT, I2C1, I2C2};
 
 /// I2C error
@@ -105,7 +105,7 @@ impl<PINS> I2c<I2C1, PINS> {
         mapr: &mut MAPR,
         mode: Mode,
         clocks: Clocks,
-        apb: &mut APB1,
+        apb: &mut <I2C1 as RccBus>::Bus,
     ) -> Self
     where
         PINS: Pins<I2C1>,
@@ -122,7 +122,7 @@ impl<PINS> BlockingI2c<I2C1, PINS> {
         mapr: &mut MAPR,
         mode: Mode,
         clocks: Clocks,
-        apb: &mut APB1,
+        apb: &mut <I2C1 as RccBus>::Bus,
         start_timeout_us: u32,
         start_retries: u8,
         addr_timeout_us: u32,
@@ -147,7 +147,13 @@ impl<PINS> BlockingI2c<I2C1, PINS> {
 }
 
 impl<PINS> I2c<I2C2, PINS> {
-    pub fn i2c2(i2c: I2C2, pins: PINS, mode: Mode, clocks: Clocks, apb: &mut APB1) -> Self
+    pub fn i2c2(
+        i2c: I2C2,
+        pins: PINS,
+        mode: Mode,
+        clocks: Clocks,
+        apb: &mut <I2C2 as RccBus>::Bus
+    ) -> Self
     where
         PINS: Pins<I2C2>,
     {
@@ -161,7 +167,7 @@ impl<PINS> BlockingI2c<I2C2, PINS> {
         pins: PINS,
         mode: Mode,
         clocks: Clocks,
-        apb: &mut APB1,
+        apb: &mut <I2C2 as RccBus>::Bus,
         start_timeout_us: u32,
         start_retries: u8,
         addr_timeout_us: u32,
@@ -352,7 +358,7 @@ macro_rules! hal {
                     pins: PINS,
                     mode: Mode,
                     clocks: Clocks,
-                    apb: &mut APB1,
+                    apb: &mut <$I2CX as RccBus>::Bus,
                     start_timeout_us: u32,
                     start_retries: u8,
                     addr_timeout_us: u32,

src/pwm_input.rs

@@ -17,7 +17,7 @@ use crate::pac::TIM4;
 
 use crate::afio::MAPR;
 use crate::gpio::{self, Floating, Input};
-use crate::rcc::{Clocks, GetBusFreq, RccBus};
+use crate::rcc::{Clocks, GetBusFreq, sealed::RccBus};
 use crate::time::Hertz;
 use crate::timer::Timer;
 

src/rcc.rs

@@ -496,20 +496,23 @@ impl GetBusFreq for APB2 {
     }
 }
 
-/// Bus associated to peripheral
-pub trait RccBus {
-    /// Bus type;
-    type Bus;
+pub(crate) mod sealed {
+    /// Bus associated to peripheral
+    pub trait RccBus {
+        /// Bus type;
+        type Bus;
+    }
 }
+use sealed::RccBus;
 
 /// Enable/disable peripheral
-pub(crate) trait Enable: RccBus {
+pub trait Enable: RccBus {
     fn enable(apb: &mut Self::Bus);
     fn disable(apb: &mut Self::Bus);
 }
 
 /// Reset peripheral
-pub(crate) trait Reset: RccBus {
+pub trait Reset: RccBus {
     fn reset(apb: &mut Self::Bus);
 }
 

src/serial.rs

@@ -54,7 +54,7 @@ use crate::gpio::gpiob::{PB10, PB11, PB6, PB7};
 use crate::gpio::gpioc::{PC10, PC11};
 use crate::gpio::gpiod::{PD5, PD6, PD8, PD9};
 use crate::gpio::{Alternate, Floating, Input, PushPull};
-use crate::rcc::{RccBus, Clocks, Enable, Reset, GetBusFreq};
+use crate::rcc::{sealed::RccBus, Clocks, Enable, Reset, GetBusFreq};
 use crate::time::{U32Ext, Bps};
 
 /// Interrupt event