Rename Verilog generation

Makefile

@@ -3,7 +3,7 @@ all: doit test
 
 # Generate Verilog code
 doit:
-	sbt "runMain s4noc.S4nocTrafficGen 9"
+	sbt "runMain s4noc.S4NoCVerilogGen 9"
 
 # Run the tests
 

src/main/scala/s4noc/S4nocTrafficGen.scala → src/main/scala/s4noc/S4NoCVerilogGen.scala

@@ -1,5 +1,5 @@
 /*
-  Traffic generator for synthesize results of a stand alone S4NOC.
+  Dummy traffic generator for synthesize results of a stand alone S4NOC.
 
   Author: Martin Schoeberl (martin@jopdesign.com)
   license see LICENSE
@@ -8,7 +8,7 @@ package s4noc
 
 import chisel3._
 
-class S4nocTrafficGen(conf: Config) extends Module {
+class S4NoCVerilogGen(conf: Config) extends Module {
 
   val s4noc = Module(new S4NoCTop(conf))
   // This is almost Chisel 3 syntax.
@@ -27,6 +27,7 @@ class S4nocTrafficGen(conf: Config) extends Module {
     s4noc.io.cpuPorts(i).address := cntReg(7, 2)
     s4noc.io.cpuPorts(i).wrData := cntReg(conf.width+7, 8)
     s4noc.io.cpuPorts(i).wr := cntReg(0)
+    s4noc.io.cpuPorts(i).wrMask := 0xf.U
     s4noc.io.cpuPorts(i).rd := cntReg(1)
     // Have some registers before or reduce
     if (i == 0) {
@@ -41,7 +42,7 @@ class S4nocTrafficGen(conf: Config) extends Module {
   io.data := RegNext(outReg(conf.n-1))
 }
 
-object S4nocTrafficGen extends App {
-  println("Generating the S4NoC hardware with a traffic generator")
-  emitVerilog(new S4nocTrafficGen(Config(args(0).toInt, BubbleType(8), BubbleType(8), BubbleType(8), 32)), Array("--target-dir", "generated"))
+object S4NoCVerilogGen extends App {
+  println("Generating the S4NoC hardware with a dummy traffic generator")
+  emitVerilog(new S4NoCVerilogGen(Config(args(0).toInt, BubbleType(8), BubbleType(8), BubbleType(8), 32)), Array("--target-dir", "generated"))
 }