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de2-115

Here are 30 public repositories matching this topic...

delhatch / Spectrum

Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

fpga audio-analysis verilog spectrum-analyzer fft altera rtaudio vga de2-115 vga-frame-buffer

Updated Feb 9, 2018
VHDL

Goshik92 / FFTVisualizer

This project demonstrates DSP capabilities of Terasic DE2-115

fpga dsp fft vga fir-filter de2-115 iir-filter

Updated Jun 22, 2018
Verilog

Goshik92 / multicore-nios

Matrix multiplication on multiple Nios II cores

fpga parallel-computing matrix-multiplication verilog mailbox nios shared-memory hdl fpga-soc qsys parallel-programming nios2 de2-115 quartus spmd sopc platform-designer

Updated Feb 12, 2020
C

delhatch / Red_Tracker

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

fpga image-processing verilog altera vga de2-115 vga-controller

Updated Jan 19, 2018
Verilog

ChienKaiMa / HDR-Imaging-with-FPGA

High Dynamic Range imaging with Altera DE2-115.

fpga vga hdr de2-115 hdr-image

Updated Mar 1, 2021
SystemVerilog

delhatch / Pure_Mandel

FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.

fpga verilog mandelbrot altera vga de2-115 vga-controller mandel

Updated Feb 9, 2018
Verilog

snwjas / DE2-Electric-Timer

DE2简易电子计时器，使用VHDL语言开发，在DE2-115开发板上测试运行通过。该电子计时器具有四种工作模式：正常计时、从外部设置当前的小时数、从外部设置当前的分钟数、从外部设置当前的秒数，同时具有可逆的计时功能。

fpga vhdl eda de2-115

Updated Jun 13, 2021
VHDL

coldnew-examples / DE2-115-Led-Blink

Simple LED blink example for DE2-115

verilog de2-115 quartus

Updated Jun 6, 2018
Verilog

Goshik92 / Thesis

Дипломная работа специалиста за 2015 год на тему "Акустическая система мониторинга на основе пространственной фильтрации звуковых сигналов".

latex fpga beamforming microphone-array de2-115 mp45dt02 sigma-delta-modulation acoustic-camera

Updated Nov 28, 2017
TeX

de2115-simple-mips-without-pipeline

mateuspinto / de2115-simple-mips-without-pipeline

A complete hardware description of a non-pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA.

fpga mips systemverilog de2-115

Updated Sep 23, 2020
SystemVerilog

snwjas / DE2-Labs

EDA技术与应用，DE2实验，DE2-115开发板实验，包含了实验1-4。

vhdl eda de2-115 de2

Updated Jun 8, 2021
VHDL

SamanKhamesian / Special-Purpose-Processor

This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)

fpga state-machine controller processor vhdl gcm lcm quartus-prime de2-115

Updated Jul 18, 2019
Verilog

kerong2002 / FPGA_TETRIS

FPGA_TETRIS

fpga tetris verilog de2-115

Updated Jun 9, 2023
Verilog

fbponz / Terasic-DE2-115-NiosII-uCosII

Design for board DE2-115, microprocessor soft running a uCOS-II(Real Time Operating System). Application to test is a Lift program

real-time rtos qsys nios2 de2-115 ucos-ii quartus niosii-ucosii

Updated Mar 18, 2017
Verilog

saleh1204 / rv32im

RV32IM System-on-Chip (SoC)

fpga de2-115 rv32im

Updated Apr 8, 2022
Verilog

daytonflores / Portable-AES-In-Hardware

arduino microcontroller fpga altera sd-card cyclone-iv de2-115 quartus advanced-encryption-standard

Updated Feb 26, 2021
Verilog

snwjas / DE2-6bit-CPU

6位简易处理器的硬件设计，使用VHDL语言开发，在DE2-115开发板上运行通过。

fpga vhdl eda cpld de2-115

Updated Jun 10, 2021
VHDL

sameer / DE2-115-template

HDLMake template for terasIC DE2-115

template vhdl verilog de2-115 hdlmake

Updated Feb 6, 2020
Tcl

delhatch / Flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

fpga verilog altera de2-115 flipdots flipdot

Updated Mar 3, 2018
Verilog

junzhengca / space-enemies

Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.

hardware project assignment verilog de2-115

Updated Jul 31, 2018
Verilog

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