Batchfile4iverilog

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)

This is an indie Electronic Fuel Injection System project that's been inherited from our sensẽi, Mr NQA. This project is a big bravo to the rest of my teammate, we've all been trying to do our best and we do.

This is a 5-day workshop on RTL Design and Synthesis using open source tools for logic design, simulation, synthesis and technology mapping with Sky130 PDK. (iVerilog, GTKwave, Yosys and Sky130 technology)

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Implementación del procesador monociclo RISC-V en System Verilog.

🌱 Tool GTKWave for open FPGAs

A repo for CS 3339 students learning verilog

A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.

A sequence generator for 4-bit even numbers, implemented in Verilog.

Python framework for testing VHDL using cocotb, GHDL and GTKWave

Project to Design and Implement a 16-bit Barrel Shifter using Verilog.

Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay

This repository contains all the task done during the VSDSquadron Mini internship 2024

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

This repository deals with BCD to binary conversion using iverilog as a simulator and yosys as a synthesis tool.

Simple MIPS 16-bit CPU implemented in VHDL with an assembler in python