Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

Created in Feb 2020. A self-paced reading task interleaving with the Stroop task. Experimental design: 2 previous trial congruency (congruent Stroop vs. incongruent Stroop) x 2 current trial ambiguity (ambiguous sentence vs. unambiguous sentence). Wrote on PCIbex.

A parser for stock data of the Ibex 35 index and its components.

An open source utility to build and simulate cores.

Test enviroment to connect jigsaw devices w/ Ibex core in CHISEL & compile the design w/ CIRCT IR to analyze the dumped SV

Master 2 robotic project : viewing calibration concepts, path planing and trajectory following. Using library Ibex with python to represent robots geometric and kinetic models

Created in 2020. A self-paced reading task (followed by comprehension questions). Sentence materials borrowed from Chow & Chen (2020)

El reto trata de un proyecto de Data Science que hay que realizar en 24h donde el objetivo es realizar un modelo predicativo con la intención de predecir en precio del Ibex35

Terraform and Packer Boilerplate code with a nifty script to simplify infrastructure creation

User oriented Portfolio optimization application with several configuring options. Back test included. (IBEX35; to be expanded)

Incremental unidirectional and bidirectional graph transformations with the Democles pattern matching engine

RISC-V Ibex core with Wishbone B4 interface

An example project that utilizes caravel user space for an ibex based SoC

Testing Ibex build using Yosys and open source toolchains.

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.