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nexys4

Here are 17 public repositories matching this topic...

Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

arm cv vivado nexys4 fpga-cortex-m3

Updated Dec 8, 2019
VHDL

rossmacarthur / mawg

Modulation and Arbitrary Waveform Generator

fpga verilog nexys4

Updated Feb 16, 2021
Verilog

ilyajob05 / verilog_modules

verilog modules

synchronization fpga i2c memory timer verilog spi xilinx uart usart 7-segment xilinx-fpga nexys4 pll rmii nexys-4-spartan-3e nexys4-board

Updated May 4, 2020
Verilog

yuanbo-peng / Combination-Lock

This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.

vhdl finite-state-machine vivado digital-design debounce-button nexys4 random-numbers combination-lock multi-digits-display

Updated Jul 29, 2020
VHDL

maxislash / MazeGame

Realization of a maze game on FPGA using VHDL

fpga vhdl maze xilinx nexys4

Updated Aug 23, 2017
VHDL

ilyajob05 / verilog_SPI

SPI module for Nexys 4 Artix-7 FPGA Trainer Board

fpga verilog spi xilinx xilinx-fpga nexys4 fpga-programming nexys-4-spartan-3e artix-7 nexys4-board

Updated May 4, 2020
Verilog

smdsbz / ElevatorController

Digital Logic curriculum design - FPGA-based elevator controller

fpga verilog digital-logic nexys4

Updated Sep 26, 2018
C

devil-of-silicon-valley / One-Time-Pad-FPGA

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

otp verilog vivado one-time-pad diligent seven-segment nexys4

Updated Jun 21, 2017
Verilog

LowPassFilterFPGA

splAcharya / LowPassFilterFPGA

Designed and Implemented a low pass filter in Nexys 4 FPGA

fpga dsp matlab simulink digital-signal-processing xilinx-fpga filter-design xilinx-vivado nexys4 lowpass-filter

Updated Jul 30, 2020
VHDL

pedrovt / cr-square-root-cop

A FPGA Based Square Root Approximation Coprocessor

fpga vhdl xilinx fpga-soc fpga-accelerator nexys4 square-root

Updated Jul 13, 2020
VHDL

maxislash / 8BitProc

Implementation of an 8-bit processor on a Xilinx FPGA in VHDL

processor-architecture fpga processor vhdl xilinx nexys4

Updated Aug 23, 2017
VHDL

LCSR-lab / NetFi3

NetFI-3: Netlist Fault Injection system - Version 3

computer-science engineering thesis vhdl computer-engineering verilog vivado fault-injection netlist nexys4

Updated Jun 29, 2020
TeX

fpgaedu / ci

Continuous integration environments for FPGAedu projects

linux vagrant continuous-integration vivado digilent nexys4

Updated May 3, 2017
Ruby

damienen / ADXL362_Nexys4

This repository contains a simple accelerometer controller for the Nexys 4 board

fpga vhdl nexys4

Updated Jan 12, 2021
VHDL

alejandromdnsls / ESCOMips

microprocessor mips-architecture nexys4 vhdl-code

Updated Jun 14, 2018
C

JochiSt / Nexys4-liteeth

use the liteeth core on the Nexys4 board without SoC

vhdl nexys4 liteeth hdlmake

Updated Jun 27, 2024
Tcl

jens-j / mandelbrot

Real-time FPGA mandelbrot explorer with SNES controller and VGA output

visualization real-time video fpga vhdl snes vga nexys4

Updated Mar 21, 2019
VHDL

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