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Dump per macro verilog (overridden by final verilog output) #134

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Oct 16, 2023
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Dump per macro verilog (overridden by final verilog output) #134

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2 changes: 2 additions & 0 deletions src/main/scala/barstools/macros/MacroCompiler.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -911,6 +911,7 @@ object MacroCompiler extends App {
.execute(
Array.empty,
Seq(
OutputFileAnnotation(params.get(Verilog).get),
RunFirrtlTransformAnnotation(new VerilogEmitter),
EmitCircuitAnnotation(classOf[VerilogEmitter]),
FirrtlSourceAnnotation(circuit.serialize)
Expand All @@ -922,6 +923,7 @@ object MacroCompiler extends App {
.value
}
.mkString("\n")

val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
verilogWriter.write(verilog)
verilogWriter.close()
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