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Update SiFive submodules to CHIPS fork #1208

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Sep 1, 2022
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2 changes: 1 addition & 1 deletion .github/scripts/check-commit.sh
Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ search

submodules=("fpga-shells")
dir="fpga"
branches=("master")
branches=("main")
search

# turn off verbose printing to make this easier to read
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6 changes: 3 additions & 3 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"]
path = generators/sifive-blocks
url = https://github.com/sifive/sifive-blocks.git
url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
Expand All @@ -27,7 +27,7 @@
url = https://github.com/firesim/icenet.git
[submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache
url = https://github.com/sifive/block-inclusivecache-sifive.git
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
path = toolchains/riscv-tools/riscv-gnu-toolchain
url = https://github.com/riscv/riscv-gnu-toolchain.git
Expand Down Expand Up @@ -121,7 +121,7 @@
url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/sifive/fpga-shells.git
url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git
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