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Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3 #544
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alonamid
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[WIP] Rocket Chip Bump with Chisel 3.3) and FIRRTL 1.3
[WIP] Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3
May 5, 2020
Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch
This was referenced May 5, 2020
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alonamid
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May 8, 2020
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alonamid
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[WIP] Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3
Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3
May 13, 2020
abejgonzalez
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May 13, 2020
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LGTM for everything except the FIRRTL stuff.
colinschmidt
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May 13, 2020
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LGTM
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Related issue:
Type of change: new feature
Impact: rtl change
Release Notes
Todo