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Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3 #544

Merged
merged 19 commits into from
May 13, 2020
Merged

Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3 #544

merged 19 commits into from
May 13, 2020

Commits on May 5, 2020

  1. bump rocket chisel (3.3) and firrtl (1.3)

    @alonamid
    alonamid committed May 5, 2020
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  2. Bump sifive-blocks

    @jerryz123
    jerryz123 committed May 5, 2020
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  3. Many changes to begin the compilation with RC-1.3 

    Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.

BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.

The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork

Treadle is bumped to its release branch
    @colinschmidt
    colinschmidt committed May 5, 2020
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  4. Update stage to use Dependency instead of classof

    @colinschmidt
    colinschmidt committed May 5, 2020
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Commits on May 6, 2020

  1. Basic changes to barstools to get sim to compile

    @albert-magyar
    albert-magyar committed May 6, 2020
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Commits on May 7, 2020

  1. Increase verilator reset length

    @colinschmidt
    colinschmidt committed May 7, 2020
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  2. Connect debug clocks when debug is tied off

    @colinschmidt
    colinschmidt committed May 7, 2020
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Commits on May 11, 2020

  1. [make] Fix firrtl prerequiste lookup

    @davidbiancolin
    davidbiancolin committed May 11, 2020
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Commits on May 12, 2020

  1. Bump FireSim

    @davidbiancolin
    davidbiancolin committed May 12, 2020
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  2. Comment out Ariane from ScalaTests

    @davidbiancolin
    davidbiancolin committed May 12, 2020
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Commits on May 13, 2020

  1. sifive cache bump to RC firrtl 1.3

    @alonamid
    alonamid committed May 13, 2020
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  2. bump testchipip with buffer arg

    @alonamid
    alonamid committed May 13, 2020
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  3. bump boom and ariane to master with RC firrtl 1.3

    @alonamid
    alonamid committed May 13, 2020
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  4. Bump barstools

    @albert-magyar
    albert-magyar committed May 13, 2020
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  5. bump barstools to master with firrtl 1.3

    @alonamid
    alonamid committed May 13, 2020
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  6. Merge branch 'firrtl-1.3-RC-bump' of https://github.com/ucb-bar/chipyard 

     into firrtl-1.3-RC-bump
    @alonamid
    alonamid committed May 13, 2020
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  7. bump firesim with firrtl 1.3

    @alonamid
    alonamid committed May 13, 2020
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  8. bump treadle to master

    @alonamid
    alonamid committed May 13, 2020
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  9. extend midas examples timeout in ci

    @abejgonzalez
    abejgonzalez committed May 13, 2020
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