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Remove GenerateSimFiles and use make instead #879

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merged 9 commits into from
May 13, 2021
Merged

Remove GenerateSimFiles and use make instead #879

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1d52899
Remove GenerateSimFiles and use make instead
abejgonzalez May 6, 2021
9cdd0e1
Replace spaces with tabs
abejgonzalez May 6, 2021
95f55a6
Elaborate comments a bit more | Remove BB'ed files that are auto-copi…
abejgonzalez May 6, 2021
eb85415
Have Verilator build with unused simulation files
abejgonzalez May 6, 2021
a0de9a0
Depend on build_dir
abejgonzalez May 7, 2021
453b1b5
Fix tutorial patch
abejgonzalez May 7, 2021
2874c98
Add sim_files.f to fpga
abejgonzalez May 7, 2021
383d11c
Forgot to add testchip_tsi.* to verilator
abejgonzalez May 7, 2021
16cdc88
Small comment + org. fix | Remove extra mkdirs
abejgonzalez May 12, 2021
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8 changes: 2 additions & 6 deletions build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -183,7 +183,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO

lazy val chipyard = (project in file("generators/chipyard"))
.sourceDependency(testchipip, testchipipLib)
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, cva6, nvdla, sodor)
Expand All @@ -192,14 +192,10 @@ lazy val chipyard = (project in file("generators/chipyard"))

lazy val tracegen = (project in file("generators/tracegen"))
.sourceDependency(testchipip, testchipipLib)
.dependsOn(rocketchip, sifive_cache, boom, utilities)
.dependsOn(rocketchip, sifive_cache, boom)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

lazy val utilities = (project in file("generators/utilities"))
.sourceDependency(testchipip, testchipipLib)
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Nice. Everything I see this I have to remind myself why we need this. Glad to see it getting removed

.settings(commonSettings)

lazy val icenet = (project in file("generators/icenet"))
.sourceDependency(testchipip, testchipipLib)
.dependsOn(rocketchip)
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11 changes: 7 additions & 4 deletions common.mk
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Expand Up @@ -20,7 +20,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client"

EXTRA_GENERATOR_REQS ?=
EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS)
EXTRA_SIM_CXXFLAGS ?=
EXTRA_SIM_LDFLAGS ?=
EXTRA_SIM_SOURCES ?=
Expand Down Expand Up @@ -85,10 +85,13 @@ else
endif

#########################################################################################
# create list of simulation file inputs
# copy over bootrom files
#########################################################################################
$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS)
$(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name))
$(build_dir):
mkdir -p $@

$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
cp -f $< $@

#########################################################################################
# create firrtl file rule and variables
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15 changes: 15 additions & 0 deletions fpga/Makefile
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Expand Up @@ -73,6 +73,21 @@ default: $(mcs)
fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND)
fpga_common_script_dir := $(fpga_dir)/common/tcl

#########################################################################################
# setup misc. sim files
#########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

# copy files but ignore *.h files in *.f (match vcs)
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Are you trying to match vcs here or are you assuming that all FPGA synthesis tools will support +incdir like VCS does and you can do the same thing as you're doing for VCS? If you're really trying to match VCS, why?

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This matches what GenerateSimFiles did in the past (filter out headers). I guess another justification for doing this is that #871 is using VCS to do FPGA-level simulation.

$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))

#########################################################################################
# import other necessary rules and variables
#########################################################################################
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0 ...ities/src/main/resources/csrc/emulator.cc → ...pyard/src/main/resources/csrc/emulator.cc
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3 changes: 2 additions & 1 deletion generators/chipyard/src/main/scala/ConfigFragments.scala
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Expand Up @@ -15,6 +15,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
import freechips.rocketchip.tilelink.{HasTLBusParams}
import freechips.rocketchip.util.{AsyncResetReg, Symmetric}
import freechips.rocketchip.prci._
import freechips.rocketchip.stage.phases.TargetDirKey

import testchipip._
import tracegen.{TraceGenSystem}
Expand All @@ -36,7 +37,7 @@ import chipyard._
// -----------------------

class WithBootROM extends Config((site, here, up) => {
case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img"))
case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"))
})

// DOC include start: gpio config fragment
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1 change: 0 additions & 1 deletion generators/utilities/src/main/resources/bootrom
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This file was deleted.

143 changes: 0 additions & 143 deletions generators/utilities/src/main/scala/Simulator.scala
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This file was deleted.

6 changes: 3 additions & 3 deletions scripts/tutorial-patches/build.sbt.patch
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Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
diff --git a/build.sbt b/build.sbt
index e80b2a5..b1989d9 100644
index 3123c4b8..487fc428 100644
--- a/build.sbt
+++ b/build.sbt
@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO
lazy val chipyard = (project in file("generators/chipyard"))
.sourceDependency(testchipip, testchipipLib)
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+// sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, cva6, nvdla, sodor)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
@@ -223,11 +223,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

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3 changes: 3 additions & 0 deletions sims/common-sim-flags.mk
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Expand Up @@ -21,3 +21,6 @@ SIM_LDFLAGS = \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)

SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
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Note: If chipsalliance/rocket-chip#2810 goes through then this is unnecessary.

15 changes: 15 additions & 0 deletions sims/vcs/Makefile
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Expand Up @@ -31,6 +31,21 @@ include $(base_dir)/vcs.mk
default: $(sim)
debug: $(sim_debug)

#########################################################################################
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v

# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))

#########################################################################################
# import other necessary rules and variables
#########################################################################################
Expand Down
35 changes: 33 additions & 2 deletions sims/verilator/Makefile
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Expand Up @@ -30,6 +30,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug

WAVEFORM_FLAG=-v$(sim_out_name).vcd

include $(base_dir)/sims/common-sim-flags.mk

# If verilator seed unspecified, verilator uses srand as random seed
ifdef RANDOM_SEED
SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
Expand All @@ -41,6 +43,37 @@ endif
default: $(sim)
debug: $(sim_debug)

#########################################################################################
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \

# the following files are needed for emulator.cc to compile
SIM_FILE_REQS += \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
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$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc

# copy files and add -FI for *.h files in *.f
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))

#########################################################################################
# import other necessary rules and variables
#########################################################################################
Expand Down Expand Up @@ -141,8 +174,6 @@ VERILATOR_NONCC_OPTS = \
#----------------------------------------------------------------------------------------
# gcc configuration/optimization
#----------------------------------------------------------------------------------------
include $(base_dir)/sims/common-sim-flags.mk

VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
Expand Down
13 changes: 10 additions & 3 deletions variables.mk
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Expand Up @@ -106,9 +106,12 @@ endif
#########################################################################################
# path to rocket-chip and testchipip
#########################################################################################
ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip
TESTCHIP_DIR = $(base_dir)/generators/testchipip
CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl
ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip
ROCKETCHIP_RSRCS_DIR = $(ROCKETCHIP_DIR)/src/main/resources
TESTCHIP_DIR = $(base_dir)/generators/testchipip
TESTCHIP_RSRCS_DIR = $(TESTCHIP_DIR)/src/main/resources
CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl
CHIPYARD_RSRCS_DIR = $(base_dir)/generators/chipyard/src/main/resources

#########################################################################################
# names of various files needed to compile and run things
Expand All @@ -135,7 +138,11 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir

BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img
BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))

# files that contain lists of files needed for VCS or Verilator simulation
SIM_FILE_REQS =
sim_files ?= $(build_dir)/sim_files.f
sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
Expand Down