Remove GenerateSimFiles and use make instead

build.sbt

@@ -183,7 +183,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO
 
 lazy val chipyard = (project in file("generators/chipyard"))
   .sourceDependency(testchipip, testchipipLib)
-  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
+  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsptools`,
     gemmini, icenet, tracegen, cva6, nvdla, sodor)
@@ -192,14 +192,10 @@ lazy val chipyard = (project in file("generators/chipyard"))
 
 lazy val tracegen = (project in file("generators/tracegen"))
   .sourceDependency(testchipip, testchipipLib)
-  .dependsOn(rocketchip, sifive_cache, boom, utilities)
+  .dependsOn(rocketchip, sifive_cache, boom)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val utilities = (project in file("generators/utilities"))
-  .sourceDependency(testchipip, testchipipLib)
-  .settings(commonSettings)
-
 lazy val icenet = (project in file("generators/icenet"))
   .sourceDependency(testchipip, testchipipLib)
   .dependsOn(rocketchip)

common.mk

@@ -20,7 +20,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_REQS         = additional make requirements to build the simulator" \
 "   ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client"
 
-EXTRA_GENERATOR_REQS ?=
+EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS)
 EXTRA_SIM_CXXFLAGS   ?=
 EXTRA_SIM_LDFLAGS    ?=
 EXTRA_SIM_SOURCES    ?=
@@ -85,10 +85,10 @@ else
 endif
 
 #########################################################################################
-# create list of simulation file inputs
+# copy over bootrom files
 #########################################################################################
-$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS)
-	$(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name))
+$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
+	cp -f $< $@
 
 #########################################################################################
 # create firrtl file rule and variables

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -15,6 +15,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 import freechips.rocketchip.tilelink.{HasTLBusParams}
 import freechips.rocketchip.util.{AsyncResetReg, Symmetric}
 import freechips.rocketchip.prci._
+import freechips.rocketchip.stage.phases.TargetDirKey
 
 import testchipip._
 import tracegen.{TraceGenSystem}
@@ -36,7 +37,7 @@ import chipyard._
 // -----------------------
 
 class WithBootROM extends Config((site, here, up) => {
-  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img"))
+  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"))
 })
 
 // DOC include start: gpio config fragment

sims/common-sim-flags.mk

@@ -21,3 +21,6 @@ SIM_LDFLAGS = \
 	-lfesvr \
 	-ldramsim \
 	$(EXTRA_SIM_LDFLAGS)
+
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

sims/vcs/Makefile

@@ -31,6 +31,22 @@ include $(base_dir)/vcs.mk
 default: $(sim)
 debug: $(sim_debug)
 
+#########################################################################################
+# simulaton requirements
+#########################################################################################
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
+
+# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
+$(sim_files): $(SIM_FILE_REQS)
+	mkdir -p $(dir $(sim_files))
+	cp -f $^ $(build_dir)
+	$(foreach file,\
+		$^,\
+		$(if $(filter %.h,$(file)),\
+			,\
+			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+
 #########################################################################################
 # import other necessary rules and variables
 #########################################################################################

sims/verilator/Makefile

@@ -30,6 +30,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
 
 WAVEFORM_FLAG=-v$(sim_out_name).vcd
 
+include $(base_dir)/sims/common-sim-flags.mk
+
 # If verilator seed unspecified, verilator uses srand as random seed
 ifdef RANDOM_SEED
 SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
@@ -41,6 +43,23 @@ endif
 default: $(sim)
 debug: $(sim_debug)
 
+#########################################################################################
+# simulaton requirements
+#########################################################################################
+SIM_FILE_REQS += \
+	$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
+	$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h
+
+# copy files and add -FI for *.h files in *.f
+$(sim_files): $(SIM_FILE_REQS)
+	mkdir -p $(dir $(sim_files))
+	cp -f $^ $(build_dir)
+	$(foreach file,\
+		$^,\
+		$(if $(filter %.h,$(file)),\
+			echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\
+			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+
 #########################################################################################
 # import other necessary rules and variables
 #########################################################################################
@@ -141,8 +160,6 @@ VERILATOR_NONCC_OPTS = \
 #----------------------------------------------------------------------------------------
 # gcc configuration/optimization
 #----------------------------------------------------------------------------------------
-include $(base_dir)/sims/common-sim-flags.mk
-
 VERILATOR_CXXFLAGS = \
 	$(SIM_CXXFLAGS) \
 	$(RUNTIME_PROFILING_CFLAGS) \

variables.mk

@@ -106,9 +106,12 @@ endif
 #########################################################################################
 # path to rocket-chip and testchipip
 #########################################################################################
-ROCKETCHIP_DIR      = $(base_dir)/generators/rocket-chip
-TESTCHIP_DIR        = $(base_dir)/generators/testchipip
-CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl
+ROCKETCHIP_DIR       = $(base_dir)/generators/rocket-chip
+ROCKETCHIP_RSRCS_DIR = $(ROCKETCHIP_DIR)/src/main/resources
+TESTCHIP_DIR         = $(base_dir)/generators/testchipip
+TESTCHIP_RSRCS_DIR   = $(TESTCHIP_DIR)/src/main/resources
+CHIPYARD_FIRRTL_DIR  = $(base_dir)/tools/firrtl
+CHIPYARD_RSRCS_DIR   = $(base_dir)/generators/chipyard/src/main/resources
 
 #########################################################################################
 # names of various files needed to compile and run things
@@ -135,7 +138,11 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
 HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
 HARNESS_SMEMS_FIR  ?= $(build_dir)/$(long_name).harness.mems.fir
 
+BOOTROM_FILES   ?= bootrom.rv64.img bootrom.rv32.img
+BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
+
 # files that contain lists of files needed for VCS or Verilator simulation
+SIM_FILE_REQS =
 sim_files              ?= $(build_dir)/sim_files.f
 sim_top_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.top.f
 sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f