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intel_adsp: cavs25: configure access to ALH
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For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub
RX/TX registers needs to be explicitly enabled before use.

The logic follow hardware initialization done in
SOF project sof/src/platform/intel/cavs/platform.c

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
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kv2019i authored and nashif committed May 30, 2023
1 parent d2e91c6 commit aa5b66b
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Showing 2 changed files with 15 additions and 0 deletions.
11 changes: 11 additions & 0 deletions drivers/dai/intel/alh/alh.c
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,10 @@
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>

#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
#include <adsp_shim.h>
#endif

#define DT_DRV_COMPAT intel_alh_dai
#define LOG_DOMAIN dai_intel_alh

Expand Down Expand Up @@ -75,6 +79,10 @@ static void alh_claim_ownership(void)
sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0x3), ALHASCTL);
sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0x3), ALHCSCTL);
#endif
#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
/* Allow LPGPDMA connection to Audio Link Hub */
sys_set_bits(ADSP_DSPALHO_ADDRESS, DSPALHO_ASO_FLAG | DSPALHO_CSO_FLAG);
#endif
}

static void alh_release_ownership(void)
Expand All @@ -86,6 +94,9 @@ static void alh_release_ownership(void)
sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0), ALHASCTL);
sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0), ALHCSCTL);
#endif
#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
sys_clear_bits(ADSP_DSPALHO_ADDRESS, DSPALHO_ASO_FLAG | DSPALHO_CSO_FLAG);
#endif
}


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4 changes: 4 additions & 0 deletions soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h
Original file line number Diff line number Diff line change
Expand Up @@ -145,4 +145,8 @@ struct cavs_win {
#define GENO_MDIVOSEL BIT(1)
#define GENO_DIOPTOSEL BIT(2)

#define DSPALHO_ASO_FLAG BIT(0)
#define DSPALHO_CSO_FLAG BIT(1)
#define DSPALHO_CFO_FLAG BIT(2)

#endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */

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