Refactor ARM interrupt system (Cortex-A & Cortex-R)

[stephanosio]

interrupt_controller: gic: Refactor GIC driver interface 

The current Generic Interrupt Controller (GIC) driver makes use of the
multi-level interrupt mechanism and `irq_nextlevel` public interface.

This is a less-than-ideal implementation for the following reasons:

1. The GIC is often used as the main interrupt controller for the
  Cortex-A and Cortex-R family SoCs and, in this case, it is not a 2nd
  level interrupt controller; in fact, it is the root interrupt
  controller and therefore should be treated as such.

2. The only reason for using `irq_nextlevel` here is to interface the
  architecture implementation to the interrupt controller functions.
  Since there is no nesting or multiple instances of an interrupt
  controller involved, there is really no point in adding such an
  abstraction.

3. 2nd level topology adds many unnecessary abstractions and results
  in strange coding artefacts as well as performance penalty due to
  additional branching.

This commit refactors the GIC driver interface as follows:

1. Remove the current GIC driver interface based on the multi-level
  interrupt mechanism and the `irq_nextlevel` public interface.

2. Define the GIC driver interface in
  `include/drivers/interrupt_controller/gic.h` and allow the arch
  implementation to directly invoke this interface.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

arch: arm: aarch32: Refactor interrupt interface 

The current AArch32 (Cortex-R and to-be-added Cortex-A) interrupt
system relies on the multi-level interrupt mechanism and the
`irq_nextlevel` public interface to invoke the Generic Interrupt
Controller (GIC) driver functions.

Since the GIC driver has been refactored to provide a direct interface,
in order to resolve various implementation issues described in the GIC
driver refactoring commit, the architecture interrupt control functions
are updated to directly invoke the GIC driver functions.

This commit also adds support for the Cortex-A and Cortex-R cores
(Cortex-A5, Cortex-R4/5, ...) that allow interfacing to a custom
external interrupt controller (i.e. non-GIC) by introducing the
`ARM_CUSTOM_INTERRUPT_CONTROLLER` configuration that maps the
architecture interrupt control functions to the SoC layer interrupt
control functions.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

arch: arm: aarch64: Refactor interrupt interface

The current AArch64 interrupt system relies on the multi-level
interrupt mechanism and the `irq_nextlevel` public interface to invoke
the Generic Interrupt Controller (GIC) driver functions.

Since the GIC driver has been refactored to provide a direct interface,
in order to resolve various implementation issues described in the GIC
driver refactoring commit, the architecture interrupt control functions
are updated to directly invoke the GIC driver functions.

This commit also adds support for the ARMv8 cores (e.g. Cortex-A53)
that allow interfacing to a custom external interrupt controller
(i.e. non-GIC) by mapping the architecture interrupt control functions
to the SoC layer interrupt control functions when
`ARM_CUSTOM_INTERRUPT_CONTROLLER` configuration is enabled.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>

[andrewboie]

LGTM just a minor nit

[carlocaione]

Can we add here something like:

+       /* SGIs are never available */
+       if (irq < 16)
+               return 0;
+

The problem comes from the tests/kernel/interrupt/arch.interrupt test that is failing the assert at https://github.com/zephyrproject-rtos/zephyr/blob/master/arch/common/sw_isr_common.c#L19 when irq == 0.

[stephanosio]

At least, for PL-390 and GIC-400, the SGIs (0-15) are always enabled and this is an expected behaviour (arm_gic_irq_is_enabled should report the actual enable status of the IRQ, which is true).

The real problem is that the dynamic interrupt test scans the SW ISR table for the first spurious ISR entry and this happens to be the IRQ 0, which is an SGI that cannot be disabled on the GIC-400.

IMO, this problem should be addressed separately in the issue #22670. After all, without proper GIC awareness in the interrupt test, removing the interrupt test ignore tag would only provide a false sense of security.

[carlocaione]

With this in place we can:

--- a/boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml
+++ b/boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml
@@ -9,4 +9,4 @@ toolchain:
 ram: 128
 testing:
   ignore_tags:
-    - interrupt
+    - nmi

[zephyrbot]

All checks are passing now.

Tip: The bot edits this comment instead of posting a new one, so you can check the comment's history to see earlier messages.

[stephanosio]

Rebased

[ioannisg]

I am fine with the refactoring, with the exception of mixing Kconfig-based #ifdef's

• CONFIG_ARMV...
• CONFIG_CPU_CORTEX_...

I know it is not perfect in the code, but we should rather fix the problems that continue mixing the define usage, IMHO

[ioannisg]

@stephanosio I did a pass on this PR - please take a look

[ioannisg]

Needs rebase now @stephanosio :)

[stephanosio]

Rebased