cpu/gd32v: add pm_layered support in periph_pm #19187

gschorcht · 2023-01-22T15:47:42Z

Contribution description

This PR provides the pm_layered support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.

Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs.

Testing procedure

The best way to test it is to rebase this PR onto PR #19186 and to flash tests/periph_pm to any GD32VF103 board. Note: The Sipeed Longan Nano works also with seeedstudio-gd32 board definition and could be used for testing.

BOARD=seeedstudio-gd32 make -C tests/periph_pm flash

The test output should be:

main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test)
...
mode 0 blockers: 1 
mode 1 blockers: 2 
mode 2 blockers: 0 
Lowest allowed mode: 2

Using command the set_rtc 1 5 command should let the MCU deep sleep for 5 seconds

> set_rtc 1 5
Setting power mode 1 for 5 seconds.
␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀>

while command set_rtc 1 5 should set the MCU into the standby mode which is left with restart.

> set_rtc 0 5
Setting power mode 0 for 5 seconds.
main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test)
...
mode 0 blockers: 1 
mode 1 blockers: 2 
mode 2 blockers: 0 
Lowest allowed mode: 2
>

The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards.

Issues/PRs references

riot-ci · 2023-01-22T16:45:34Z

Murdock results

✔️ PASSED

cfbda40 cpu/gdv32: add pm_layered support

Success	Failures	Total	Runtime
6796	0	6796	09m:55s

Artifacts

Documentation preview

benpicco · 2023-01-23T01:16:28Z

cpu/gd32v/include/periph_cpu.h

+};
+
+/**
+ * @brief   Wake-up pin used


How does this work?
Can this be any pin? Can there only be one?

This is reused by STM32 and refers to the PA0/WKUP pin that all STM32 MCUs and the GD32V MCU have. That means it can be used or not, but it is not configurable. Theoretically, it should also be possible to use WFE instead of WFI for deep sleep and standby modes to wake up the MCU when toggling pins for which the EXTI line is configured for events. But we don't have a corresponding configuration infrastructure for this yet.

Ah so this would be

Set this to 1 to enable wake from Deep Sleep via PA0/WKUP

Ideally this would be a proper CONFIG_ define (also for STM32), but that could be done as a follow up.
A comment will already help a lot.

benpicco · 2023-01-23T01:17:36Z

pkg/nmsis_sdk/Makefile

@@ -0,0 +1,10 @@
+PKG_NAME=nmsis_sdk
+PKG_URL=https://github.com/Nuclei-Software/NMSIS.git


heh, totally not CMSIS 😄

benpicco · 2023-01-23T19:03:07Z

cpu/gd32v/include/periph_cpu.h

+ */
+enum {
+    GD32V_PM_STANDBY = 0,       /**< STANDBY mode,  */
+    GD32V_PM_DEEPSLEEP = 1,     /**< DEEPSLEEP mode, corresponds to STOP mode of STM32 */


Wait, Deep Sleep is higher than standby?

Yes, sounds strange but it is the case. In STM32 terminology the GDV32 DEEPSLEEP mode is called STOP mode.

RIOT/cpu/stm32/include/periph/cpu_pm.h

Lines 37 to 43 in 7157ff3

/**

* @name Power modes

* @{

*/

#define STM32_PM_IDLE (2U) /**< Index of IDLE mode */

#define STM32_PM_STOP (1U) /**< Index of STOP mode */

#define STM32_PM_STANDBY (0U) /**< Index of STANDBY mode */

From DEEPSLEEP/STOP mode, the MCU can be woken up without reboot, from STANDBY mode it can only be woken up with restart.

hm that's the opposite of what I would expect, on other MCUs Deep Sleep means wakeing up involves a reset and only RTC memory is retained whereas Standby retains RAM.

Is that the official terminology on this platform?

on other MCUs Deep Sleep means wakeing up involves a reset and only RTC memory is retained whereas Standby retains RAM.

Exactly, that was what I expected too. But this the official terminology for GD32V and for STM32.

See User Manual, section 3.3.4, page 50f

better add a comment for clarification as to what the modes do

benpicco

Please squash

benpicco · 2023-01-23T22:07:40Z

bors merge

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-01-23T22:12:16Z

Build failed (retrying...):

Murdock

bors · 2023-01-23T22:19:56Z

Canceled.

benpicco · 2023-01-23T22:32:33Z

bors merge

19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

benpicco · 2023-01-23T22:35:45Z

bors cancel

bors merge

bors · 2023-01-23T22:35:47Z

Canceled.

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-01-23T22:41:31Z

Build failed (retrying...):

Murdock

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-01-23T23:31:34Z

Build failed (retrying...):

Murdock

19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-01-23T23:49:44Z

Canceled.

The GD32V MCU is a Nuclei-based RISC-V MCU. The NMSIS SDK provides some basic functions for the access to control and status registers of such MCUs.

gschorcht · 2023-01-24T13:48:33Z

bors merge

bors · 2023-01-24T17:08:31Z

Build succeeded:

gschorcht requested review from kaspar030, leandrolanzieri, jia200x and MrKevinWeiss as code owners January 22, 2023 15:47

gschorcht requested a review from bergzand January 22, 2023 15:47

github-actions bot added Area: cpu Area: CPU/MCU ports Area: doc Area: Documentation Area: Kconfig Area: Kconfig integration Area: pkg Area: External package ports labels Jan 22, 2023

benpicco reviewed Jan 23, 2023

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github-actions bot removed the Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms label Jan 23, 2023

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gschorcht force-pushed the cpu/gd32v/periph_pm branch from 615c2a0 to 25afe30 Compare January 23, 2023 21:40

gschorcht force-pushed the cpu/gd32v/periph_pm branch from 25afe30 to 13ad9fe Compare January 23, 2023 22:19

gschorcht added 3 commits January 24, 2023 00:52

pkg/nmsis_sdk: add NMSIS SDK for Nuclei-based MCUs

7c6a0de

The GD32V MCU is a Nuclei-based RISC-V MCU. The NMSIS SDK provides some basic functions for the access to control and status registers of such MCUs.

cpu/gd32v: use NMSIS SDK package

b02ffb2

cpu/gdv32: add pm_layered support

cfbda40

gschorcht force-pushed the cpu/gd32v/periph_pm branch from cf9c8b7 to cfbda40 Compare January 23, 2023 23:52

bors bot merged commit f85366a into RIOT-OS:master Jan 24, 2023

gschorcht deleted the cpu/gd32v/periph_pm branch January 24, 2023 20:30

MrKevinWeiss added this to the Release 2023.04 milestone Apr 25, 2023

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cpu/gd32v: add pm_layered support in periph_pm #19187

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		@@ -0,0 +1,10 @@
		PKG_NAME=nmsis_sdk
		PKG_URL=https://github.com/Nuclei-Software/NMSIS.git

	/**
	* @name Power modes
	* @{
	*/
	#define STM32_PM_IDLE (2U) /*< Index of IDLE mode /
	#define STM32_PM_STOP (1U) /*< Index of STOP mode /
	#define STM32_PM_STANDBY (0U) /*< Index of STANDBY mode /

cpu/gd32v: add pm_layered support in periph_pm #19187

cpu/gd32v: add pm_layered support in periph_pm #19187

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