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refactor Timer to chisel3. #3078

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SingularityKChen
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Type of change: other enhancement

Impact: no functional change

Development Phase: implementation

Release Notes

Refactor Timer.scala to chisel3 style.

@SingularityKChen SingularityKChen changed the base branch from master to chisel3_port September 30, 2022 08:35
@sequencer sequencer merged commit efd3151 into chipsalliance:chisel3_port Oct 2, 2022
@sequencer sequencer mentioned this pull request Oct 2, 2022
@SingularityKChen SingularityKChen deleted the porting-Timer branch October 3, 2022 03:18
sequencer pushed a commit that referenced this pull request Oct 3, 2022
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Oct 3, 2022
sequencer added a commit that referenced this pull request Oct 4, 2022
* feat: convert groundtest to chisel3 (#3048)
* refactor util/package to chisel3. (#3050)
* refactor TLBPermissions to chisel3. (#3055)
* refactor ICache to chisel3. (#3064)
* refactor PTW to chisel3. (#3067)
* refactor CSR to chisel3. (#3068)
* refactor Timer to chisel3. (#3078)
* refactor DCache to chisel3. (#3077)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: SingularityKChen <chency_singularity@163.com>
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2 participants