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Merging chisel3_port into master #3097

Merged
merged 8 commits into from
Oct 4, 2022
Merged

Merging chisel3_port into master #3097

merged 8 commits into from
Oct 4, 2022

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tianrui-wei
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Sequential Equivalence Checking using jaspergold shows that the current chisel3 port f8d19c289942d8118048a816cb323ae5270380a8 is equivalent to 7c1f50691950e43e530b14263cf2706983a5a9f8

tianrui-wei and others added 8 commits October 3, 2022 14:31
feat: convert groundtest to chisel3
wrap io declaration and use explicit import

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
+ DontCare s1_dout as its Mux is not fully connected;
+ + also remove "init = " (with param name) as new chisel-plugin in 3.6 won't compile;
+ change .cloneType to chiselTypeOf;
+ DontCare pma_checker.io as most of them are not connected;
+ DontCare res in func addressToProbe for partial initialization;
+ Use WireDefault for some partial initializations;
+ Change Bits to UInt;
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@sequencer sequencer left a comment

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Thanks @tianrui-wei, since #3095(b70600b) and #3096(d613bf1) is merged today morning, I reset chisel3_port to f8d19c2, and approved this PR, after CI merging it, I will rebase #3095(b70600b) and #3096(d613bf1) to the new master.

@sequencer sequencer enabled auto-merge (squash) October 4, 2022 03:58
@tianrui-wei
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Sounds great!

@sequencer sequencer merged commit 275661b into master Oct 4, 2022
@sequencer sequencer deleted the chisel3_port branch October 4, 2022 05:03
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3 participants